公开(公告)号：US20240290400A1

公开(公告)日：2024-08-29

申请号：US18312037

申请日：2023-05-04

申请人： Winbond Electronics Corp.

发明人： Ying-Shan KUO ,  Lung-Chi CHENG ,  Ju-Chieh CHENG

IPC分类号： G11C16/34 ,  G11C16/14

CPC分类号： G11C16/3445 ,  G11C16/14 ,  G11C16/3477

摘要： An erasing method of a memory device includes the following steps. It is determined whether a memory passes the first erasing verification operation according to the first erasing verification threshold. When the memory does not pass the first erasing verification operation, an erasing operation is performed on the memory. When the memory passes the first erasing verification operation, a flag is generated and it is determined whether the memory passes a second erasing verification operation according to the second erasing verification threshold. When the memory does not pass the second erasing verification operation, the erasing operation is performed on the memory. When the memory passes the second erasing verification operation, an over-erase correction is performed on the memory. It is determined whether there is a flag indicating that all addresses pass the first erasing verification to determine whether the memory passes the first or second erasing verification operation.

公开(公告)号：US09171622B2

公开(公告)日：2015-10-27

申请号：US13843846

申请日：2013-03-15

申请人： SK hynix Inc.

发明人： Young-Jun Kwon

IPC分类号： G11C16/00 ,  G11C16/04 ,  G11C16/34 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC分类号： G11C16/0441 ,  G11C16/3477 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7887

摘要： This technology provides a non-volatile memory device and a method of manufacturing the same, which may prevent an over-erase phenomenon and also increase the degree of integration, In an aspect, the non-volatile memory device includes a select gate formed over a substrate, a plurality of floating gates laterally formed with respect to the select gate and spaced apart from each other, to be independently programmable, and a plurality of junctions formed in the substrate and arranged to be controllable by the respective floating gates.

摘要翻译： 该技术提供了一种非易失性存储器件及其制造方法，其可以防止过度擦除现象并且还增加集成度。一方面，非易失性存储器件包括形成在 衬底，相对于选择栅极横向形成并且彼此分开的多个浮动栅极可独立编程，以及形成在衬底中并被布置成可由相应浮动栅极控制的多个结。

公开(公告)号：US08416630B2

公开(公告)日：2013-04-09

申请号：US13342834

申请日：2012-01-03

申请人： Alberto Pesavento ,  John D. Hyde

发明人： Alberto Pesavento ,  John D. Hyde

IPC分类号： G11C11/34

CPC分类号： G11C16/0433 ,  G11C11/005 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2216/10 ,  G11C2216/26

摘要： A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

摘要翻译： 使用其源极连接到电源（Vdd）的浮栅pFET读出晶体管构造非易失性存储单元，其漏极提供电流，其可以被感测以确定单元的状态。 pFET读出晶体管的栅极提供电荷存储，可用于表示诸如二进制位之类的信息。 耦合在第一电压源和浮动栅极之间的控制电容器和在第二电压源和浮置栅极之间的隧道电容器被制造成使得控制电容器具有比隧道电容器多得多的电容。 施加到第一电压源和第二电压源的电压的操作控制电容器结构和pFET电介质两端的电场，从而Fowler-Nordheim隧穿电子在浮栅上和离开浮栅，控制浮栅上的电荷和信息 存储在其上。

公开(公告)号：US20110051524A1

公开(公告)日：2011-03-03

申请号：US12806848

申请日：2010-08-23

申请人： Fu-Chang Hsu ,  Peter W. Lee

发明人： Fu-Chang Hsu ,  Peter W. Lee

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/0458 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/10 ,  G11C16/16 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C16/3477 ,  G11C2211/5621

摘要： A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to a first programmed threshold voltage level, and programming the other of the two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to the first programmed threshold voltage level or to a second programmed threshold voltage level. Combinations of the erased threshold voltage level and the first and second programmed threshold voltage levels determine an internal data state of the NAND-like dual charge retaining transistor NOR flash memory cells which are then decoded to ascertain the external data logical state.

摘要翻译： 用于NAND类型的双电荷保持晶体管NOR闪存单元的操作的方法和装置开始于擦除，验证将擦除的电荷保持晶体管的阈值电压电平擦除为已擦除的阈值电压电平。 然后，通过将NAND类双电荷保持晶体管NOR闪存单元的两个电荷保持晶体管中的一个编程为第一编程阈值电压电平，并编程NAND类似的双电荷保持的两个电荷保持晶体管中的另一个来进行方法 晶体管NOR闪存单元到第一编程阈值电压电平或第二编程阈值电压电平。 擦除阈值电压电平和第一和第二编程阈值电压电平的组合确定NAND类似的双电荷保持晶体管NOR闪存单元的内部数据状态，然后对其进行解码以确定外部数据逻辑状态。

公开(公告)号：US07804713B2

公开(公告)日：2010-09-28

申请号：US12234734

申请日：2008-09-22

申请人： Allan Parker

发明人： Allan Parker

IPC分类号： G11C16/04

CPC分类号： G11C16/0475 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5641 ,  H01L27/11568

摘要： Flash memory systems and methodologies are provided herein for providing byte alterability in a flash device. Logical cell mapping is changed from using a single physical memory cell to using two adjacent physical cells as a logical cell for emulating byte alterability. By mapping two adjacent physical cells as a single logical cell, the logical cell is a combination of neighboring drain/source regions, thereby creating a single program and erase entity. The single program and erase entities can allow for logical cell erase and program in either direction of a low voltage state or a high voltage state on a single bit or variable bit length basis. By employing the single program and erase entity, the subject innovation can provide a cost-effective approach to emulating electrically EEPROM in a flash device.

摘要翻译： 本文提供了闪存系统和方法，用于在闪存设备中提供字节可变性。 逻辑单元映射从使用单个物理存储器单元改变为使用两个相邻的物理单元作为用于模拟字节可变性的逻辑单元。 通过将两个相邻的物理单元映射为单个逻辑单元，逻辑单元是相邻的漏极/源极区域的组合，由此创建单个的程序和擦除实体。 单个程序和擦除实体可以允许在单个位或可变位长度的基础上在低电压状态或高电压状态的任一方向上进行逻辑单元擦除和编程。 通过采用单个程序和擦除实体，本发明可以提供在闪存器件中仿真电EEPROM的成本有效的方法。

公开(公告)号：US07791954B2

公开(公告)日：2010-09-07

申请号：US12234736

申请日：2008-09-22

申请人： Allan Parker

发明人： Allan Parker

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5635 ,  G11C16/0475 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2211/5641 ,  H01L27/11568

摘要： Flash memory systems and methodologies are provided herein for facilitating a single logical cell erasure and dynamic erase state. The single logical cell erasure can be accomplished on a basis of a single program and erase entity which is a combination of neighboring drain/source regions of two adjacent physical memory cells. The dynamic erase state can involve an indicator bit that indicates an erase direction of a low voltage state or a high voltage state. The single logical cell erasure can be performed by changing a voltage state of a single program and erase entity according to the indicated erase direction. By employing the indicator bit with the single program and erase entity decoding scheme, the methods and systems can reduce erase time and/or a number of cycles, thereby increasing system reliability, efficiency, and/or durability.

摘要翻译： 本文提供了闪存系统和方法，以便于单个逻辑单元擦除和动态擦除状态。 单个逻辑单元擦除可以基于作为两个相邻物理存储器单元的相邻漏极/源极区域的组合的单个程序和擦除实体来完成。 动态擦除状态可以包括指示低电压状态或高电压状态的擦除方向的指示符位。 可以通过根据指示的擦除方向改变单个程序和擦除实体的电压状态来执行单个逻辑单元擦除。 通过采用具有单个编程和擦除实体解码方案的指示符位，方法和系统可以减少擦除时间和/或多个周期，从而提高系统的可靠性，效率和/或耐久性。

公开(公告)号：US20100014355A1

公开(公告)日：2010-01-21

申请号：US12571917

申请日：2009-10-01

申请人： Motoharu Ishii ,  Seiichi Endo

发明人： Motoharu Ishii ,  Seiichi Endo

IPC分类号： G11C16/04

CPC分类号： G11C16/3468 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477 ,  H01L27/11526 ,  H01L27/11529

摘要： In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.

摘要翻译： 在非易失性存储单元中，选择晶体管串联连接到存储单元晶体管。 选择晶体管形成双层栅极结构，并且每个栅极的电压分别驱动。 使用选择晶体管的这些叠层栅极电极层之间的电容耦合，将选择晶体管的栅极电位设置为预定电压电平。 可以使由电压发生器对选择晶体管的栅极产生的电压电平的绝对值较小，从而可以减少电流消耗，并且可以减小电压发生器的布局面积。 因此，提供了具有低电流消耗和小芯片布局面积的非易失性半导体存储器件。

公开(公告)号：US20090296492A1

公开(公告)日：2009-12-03

申请号：US12132153

申请日：2008-06-03

申请人： Chung Zen Chen

发明人： Chung Zen Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477

摘要： A method for erasing flash memory comprises the steps of: setting a critical ending condition; simultaneously erasing selected multiple sectors of the flash memory; stopping simultaneous erasing if one of the selected multiple sectors meets the critical ending condition; and erasing the remainder of each of the selected multiple sectors sequentially.

摘要翻译： 一种擦除闪速存储器的方法包括以下步骤：设置临界结束条件; 同时擦除闪存的所选择的多个扇区; 如果所选择的多个扇区之一满足临界结束条件，则停止同时擦除; 并且顺序地擦除所选择的多个扇区中的每一个的剩余部分。

公开(公告)号：US07548463B2

公开(公告)日：2009-06-16

申请号：US11802322

申请日：2007-05-22

申请人： Kazuo Watanabe ,  Hiroshi Sugawara

发明人： Kazuo Watanabe ,  Hiroshi Sugawara

IPC分类号： G11C16/06

CPC分类号： G11C16/16 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477

摘要： A nonvolatile semiconductor memory device includes a memory array and an X-decode section. The memory array includes a plurality of nonvolatile memory cells arranged in a matrix form and a plurality of word lines. The X-decode section selects a selected word line selected from the plurality of word lines, supplies a negative voltage to the selected word line, and supplies a positive voltage to unselected word lines which are not the selected word line, at the time of an erase operation.

摘要翻译： 非易失性半导体存储器件包括存储器阵列和X解码部分。 存储器阵列包括以矩阵形式布置的多个非易失性存储单元和多个字线。 X解码部选择从多个字线选择的所选择的字线，向所选择的字线提供负电压，并将正电压提供给不是所选字线的未选字线， 擦除操作。

公开(公告)号：US07477546B2

公开(公告)日：2009-01-13

申请号：US12021255

申请日：2008-01-28

申请人： Gang-feng Fang ,  Wingyu Leung

发明人： Gang-feng Fang ,  Wingyu Leung

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： H01L27/115 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/3477 ,  G11C2216/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558

摘要： A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.