公开(公告)号：US5864252A

公开(公告)日：1999-01-26

申请号：US800195

申请日：1997-02-13

Applicant: Thinh Dinh Tran ,  Tsu-Wei Frank Lee

Inventor： Thinh Dinh Tran ,  Tsu-Wei Frank Lee

IPC: H03K3/289

CPC classification number: H03K5/135 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066

Abstract: A synchronous circuit, such as an SRAM, a DRAM or a programmable logic device, has internal circuitry, a master input latch clocked by a master clock generator, and a slave output latch clocked by a slave clock generator. The master input latch is rendered transparent prior to the start of system setup time so that information input signals can pass through the master input latch and undergo processing in the circuitry prior to the start of a system cycle. After correct and stable information output signals are generated by the internal circuitry, these signals are latched into the slave output latch as correct and stable output information. The master latch may be clocked from the latched to the transparent state before the slave latch is clocked from the transparent to the latched state, provided that the time period between these two transitions is less than the minimum processing time of the internal circuitry. By advancing the start of the internal signal processing by a time period equal to the system setup time, the system clock to data output access time is substantially shortened.

Abstract translation: 诸如SRAM，DRAM或可编程逻辑器件的同步电路具有内部电路，由主时钟发生器计时的主输入锁存器和由时钟发生器提供时钟的从输出锁存器。 在系统建立时间开始之前，主输入锁存器变为透明的，以便信息输入信号可以通过主输入锁存器并在系统周期开始之前在电路中进行处理。 在由内部电路产生正确和稳定的信息输出信号后，这些信号被锁存到从输出锁存器中作为正确和稳定的输出信息。 如果这两个转换之间的时间间隔小于内部电路的最小处理时间，则从锁存器从透明时钟到锁存状态，主锁存器可以从锁存时钟到透明状态。 通过将内部信号处理的开始推进到与系统建立时间相同的时间段，系统时钟到数据输出访问时间显着缩短。

公开(公告)号：US07728619B1

公开(公告)日：2010-06-01

申请号：US12059953

申请日：2008-03-31

Applicant: Joseph Jengtao Tzou ,  Suresh Parameswaran ,  Thinh Dinh Tran

Inventor： Joseph Jengtao Tzou ,  Suresh Parameswaran ,  Thinh Dinh Tran

IPC: H03K17/16

CPC classification number: H04L25/0278

Abstract: An improved circuit and method for programmable cascading of impedance matching in a multi-chip configuration are disclosed. Handshaking is implemented in cascaded chips by defining a master-slave configuration, and impedance is evaluated in cascaded chips in a non-overlapping manner. The circuit includes a plurality of chips arranged in a cascading configuration. A cascade output pin of a chip is coupled to a cascade input pin of a cascaded chip to enable handshaking between the plurality of chips. The plurality of chips are coupled to a common precision resistor via a common impedance line to enable each chip to calibrate impedance of the chip. Each of the plurality of chips includes a control circuit. Each control circuit includes a state machine circuit. The control circuit is configured to control a non-overlapping clock cycle of each chip during which the impedance of the chip is evaluated.

Abstract translation: 公开了一种用于多芯片配置中的阻抗匹配的可编程级联的改进的电路和方法。 通过定义主从配置来实现级联芯片中的握手，并以不重叠的方式对级联芯片进行阻抗评估。 该电路包括以级联配置布置的多个芯片。 芯片的级联输出引脚耦合到级联芯片的级联输入引脚，以实现多个芯片之间的握手。 多个芯片通过公共阻抗线耦合到公共精密电阻器，以使得每个芯片能够校准芯片的阻抗。 多个芯片中的每一个包括控制电路。 每个控制电路包括状态机电路。 控制电路被配置为控制芯片的阻抗被评估的每个芯片的非重叠时钟周期。