公开(公告)号：US07728619B1

公开(公告)日：2010-06-01

申请号：US12059953

申请日：2008-03-31

Applicant: Joseph Jengtao Tzou ,  Suresh Parameswaran ,  Thinh Dinh Tran

Inventor： Joseph Jengtao Tzou ,  Suresh Parameswaran ,  Thinh Dinh Tran

IPC: H03K17/16

CPC classification number: H04L25/0278

Abstract: An improved circuit and method for programmable cascading of impedance matching in a multi-chip configuration are disclosed. Handshaking is implemented in cascaded chips by defining a master-slave configuration, and impedance is evaluated in cascaded chips in a non-overlapping manner. The circuit includes a plurality of chips arranged in a cascading configuration. A cascade output pin of a chip is coupled to a cascade input pin of a cascaded chip to enable handshaking between the plurality of chips. The plurality of chips are coupled to a common precision resistor via a common impedance line to enable each chip to calibrate impedance of the chip. Each of the plurality of chips includes a control circuit. Each control circuit includes a state machine circuit. The control circuit is configured to control a non-overlapping clock cycle of each chip during which the impedance of the chip is evaluated.

Abstract translation: 公开了一种用于多芯片配置中的阻抗匹配的可编程级联的改进的电路和方法。 通过定义主从配置来实现级联芯片中的握手，并以不重叠的方式对级联芯片进行阻抗评估。 该电路包括以级联配置布置的多个芯片。 芯片的级联输出引脚耦合到级联芯片的级联输入引脚，以实现多个芯片之间的握手。 多个芯片通过公共阻抗线耦合到公共精密电阻器，以使得每个芯片能够校准芯片的阻抗。 多个芯片中的每一个包括控制电路。 每个控制电路包括状态机电路。 控制电路被配置为控制芯片的阻抗被评估的每个芯片的非重叠时钟周期。

公开(公告)号：US07142477B1

公开(公告)日：2006-11-28

申请号：US10871825

申请日：2004-06-18

Applicant: Thinh Tran ,  Joseph Tzou ,  Suresh Parameswaran

Inventor： Thinh Tran ,  Joseph Tzou ,  Suresh Parameswaran

IPC: G11C8/00

CPC classification number: G11C11/417 ,  G11C7/1066 ,  G11C8/18

Abstract: A memory interface system and method are provided for transferring data between a memory controller and an array of storage elements. The storage elements are preferably SRAM elements, and the memory interface is preferably one having separate address bus paths and separate data bus paths. One address bus path is reserved for receiving read addresses and the other address bus path is reserved for receiving write addresses. One of the data bus paths is reserved for receiving read data from the array, and the other data bus path is reserved for receiving data written to the array. While bifurcating the address and data bus paths within the interface is transparent to the memory controller, the separate paths afford addressing phases of a read and write address operation to be partially overlapped, as well as the data transfer phases. This will essentially reduce the cycle time between a read and write memory access, and proves useful when maximizing the data throughput across the data bus when implementing double data rate (QDR) mechanisms.

Abstract translation: 提供了一种用于在存储器控制器和存储元件阵列之间传送数据的存储器接口系统和方法。 存储元件优选地是SRAM元件，并且存储器接口优选地具有分离的地址总线路径和单独的数据总线路径。 保留一个地址总线路径用于接收读取地址，另一个地址总线路径被保留用于接收写入地址。 数据总线路径之一被保留用于从阵列接收读取数据，另一条数据总线路径被保留用于接收写入阵列的数据。 虽然分区接口内的地址和数据总线路径对于存储器控制器是透明的，但是单独的路径提供读取和写入地址操作的寻址阶段以部分重叠，以及数据传输阶段。 这将实质上减少读写存储器访问之间的周期时间，并且在实现双数据速率（QDR）机制时在数据总线上最大化数据吞吐量时被证明是有用的。

公开(公告)号：US08040164B2

公开(公告)日：2011-10-18

申请号：US12286321

申请日：2008-09-29

Applicant: Suresh Parameswaran ,  Joseph Tzou ,  Morgan Whately ,  Thinh Tran

Inventor： Suresh Parameswaran ,  Joseph Tzou ,  Morgan Whately ,  Thinh Tran

IPC: H03B1/00 ,  H03K3/00

CPC classification number: H03K19/0005 ,  H04L25/0278

Abstract: An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.

Abstract translation: 集成电路可以包括至少第一复制驱动器级，其耦合在参考阻抗输入和第一电源节点之间，并且具有与第一驱动器配置值设置的第一可编程驱动器阻抗以与第一驱动器配置值的第一输出驱动器部分相同的方式 集成电路。 至少第一复制输入终端级可以耦合在参考阻抗输入和第一电源节点之间，并且具有与集成电路的第一输入终端部分相同的方式由第一终端配置值设置的第一可编程终止阻抗 。 响应于参考节点处的电位，阻抗编程电路可产生至少第一驱动器配置值和第一终端配置值。

公开(公告)号：US07719908B1

公开(公告)日：2010-05-18

申请号：US11963446

申请日：2007-12-21

Applicant: Joseph Tzou ,  Suresh Parameswaran ,  Thinh Tran

Inventor： Joseph Tzou ,  Suresh Parameswaran ,  Thinh Tran

IPC: G11C29/00

CPC classification number: G11C29/08 ,  G11C11/41 ,  G11C29/12015 ,  G11C29/50 ,  G11C29/50012

Abstract: Embodiments of the invention relate to the testing and reduction of read disturb failures in a memory, e.g., an array of SRAM cells. A read disturb test mode may be added during wafer sort to identify any marginal memory cells that may fail read disturb, thus minimizing yield loss. The read disturb test mode may include first writing data to the memory. After a predetermined time period, the read disturb test mode reads data from the same memory, and compares the read data with the data previously written to the memory. A repair signal may be generated, when the read data is different from the data previously written to the memory. Additionally, a system may be implemented to reduce read disturb failures in the memory. The system may include a match logic circuit and a data selecting circuit. When a match condition is satisfied, data is read from a register that stores the previous written data, instead of from the memory. The match logic circuit may be selectively enabled or disabled.

Abstract translation: 本发明的实施例涉及测试和减少存储器（例如SRAM单元阵列）中的读取干扰故障。 可以在晶片排序期间添加读取干扰测试模式以识别可能失败读取干扰的任何边缘存储器单元，从而使产量损失最小化。 读取干扰测试模式可以包括首先将数据写入存储器。 在预定时间段之后，读取干扰测试模式从相同存储器读取数据，并将读取的数据与先前写入存储器的数据进行比较。 当读取的数据与先前写入存储器的数据不同时，可能会产生修复信号。 此外，可以实现系统以减少存储器中的读取干扰故障。 该系统可以包括匹配逻辑电路和数据选择电路。 当满足匹配条件时，从存储先前写入数据的寄存器中读取数据，而不是从存储器读取数据。 可以选择性地启用或禁用匹配逻辑电路。

公开(公告)号：US07535772B1

公开(公告)日：2009-05-19

申请号：US10877932

申请日：2004-06-25

Applicant: Suresh Parameswaran ,  Thinh Tran

Inventor： Suresh Parameswaran ,  Thinh Tran

IPC: G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093

Abstract: Data paths (100 and 900) can be configured to accommodate two or four burst data sequences, with a data value being input/output each half clock cycle. A data sequence can be a fixed order or user-defined order depending upon a selected option. A data input path (100) can reduce power consumption with an enable signal (dinen) timed to activate after data input lines have settled values. A data output path (900) can access output data in a parallel fashion for subsequent output according to a burst sequence. Cycle latencies for such output data can include one clock cycle latency or one and a half-clock cycles. A data output path (900) can also accommodate various clocking modes, including: single clocking with a delay locked loop (DLL) type circuit enabled, single clocking with a delay locked loop (DLL) type circuit disabled, and double clocking, with a phase difference between an input clock and output clock of up to 180°.

Abstract translation: 可以将数据路径（100和900）配置为容纳两个或四个突发数据序列，其中数据值每半个时钟周期被输入/输出。 取决于所选择的选项，数据序列可以是固定顺序或用户定义的顺序。 数据输入路径（100）可以通过在数据输入线具有稳定值之后定时激活的使能信号（dinen）来降低功耗。 数据输出路径（900）可以并行地访问输出数据，以便根据突发序列进行后续输出。 这种输出数据的周期延迟可以包括一个时钟周期延迟或一个半个时钟周期。 数据输出路径（900）还可以适应各种时钟模式，包括：启用延迟锁定环路（DLL）类型电路的单一时钟，禁用延迟锁定环路（DLL）类型电路的单时钟，双时钟 输入时钟和输出时钟之间的相位差可达180°。

公开(公告)号：US20090085614A1

公开(公告)日：2009-04-02

申请号：US12286321

申请日：2008-09-29

Applicant: Suresh Parameswaran ,  Joseph Tzou ,  Morgan Whately ,  Thinh Tran

Inventor： Suresh Parameswaran ,  Joseph Tzou ,  Morgan Whately ,  Thinh Tran

IPC: H03B1/00

CPC classification number: H03K19/0005 ,  H04L25/0278

Abstract: An integrated circuit may include at least a first replica driver stage coupled between a reference impedance input and a first power supply node and having a first programmable driver impedance set by a first driver configuration value in the same manner as a first output driver section of the integrated circuit. At least a first replica input termination stage may be coupled between the reference impedance input and the first power supply node and having a first programmable termination impedance set by a first termination configuration value in the same manner as a first input termination section of the integrated circuit. An impedance programming circuit may generate at least the first driver configuration value and the first termination configuration value in response to a potential at the reference node.

Abstract translation: 集成电路可以包括至少第一复制驱动器级，其耦合在参考阻抗输入和第一电源节点之间，并且具有与第一驱动器配置值设置的第一可编程驱动器阻抗以与第一驱动器配置值的第一输出驱动器部分相同的方式 集成电路。 至少第一复制输入终止级可以耦合在参考阻抗输入和第一电源节点之间，并具有与集成电路的第一输入终端部分相同的方式由第一终端配置值设置的第一可编程终止阻抗 。 响应于参考节点处的电位，阻抗编程电路可产生至少第一驱动器配置值和第一终端配置值。

公开(公告)号：US07403446B1

公开(公告)日：2008-07-22

申请号：US11237378

申请日：2005-09-27

Applicant: Suresh Parameswaran ,  Thinh Tran ,  Joseph Tzou

Inventor： Suresh Parameswaran ,  Thinh Tran ,  Joseph Tzou

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C11/419 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C8/18

Abstract: Synchronous SRAM may conform to Std. Sync or early-write at an external interface whilst providing late-write internally.

Abstract translation: 同步SRAM可以符合标准 在外部接口同步或提前写入，同时在内部提供后期写入。