公开(公告)号：US20070171099A1

公开(公告)日：2007-07-26

申请号：US11561184

申请日：2006-11-17

申请人： Thomas Kuenemund

发明人： Thomas Kuenemund

IPC分类号： H03M7/00

CPC分类号： G06F21/75

摘要： A circuit arrangement having complementary data lines of a dual rail data bus, wherein in a regular operating phase the complementary data lines carry complementary signals, and in a precharge phase the complementary data lines assume an identical logic state or the same electrical potential. The circuit arrangement also has a device for detecting manipulation attempts, the device having a detector circuit, which outputs an alarm signal upon the occurrence of an identical logic state on both data lines in the regular operating phase.

摘要翻译： 具有双轨数据总线的互补数据线的电路装置，其中在常规工作阶段中，互补数据线承载互补信号，并且在预充电阶段，互补数据线呈现相同的逻辑状态或相同的电位。 电路装置还具有用于检测操作尝试的装置，该装置具有检测器电路，其在正常操作阶段中在两条数据线上发生相同逻辑状态时输出报警信号。

公开(公告)号：US20130100559A1

公开(公告)日：2013-04-25

申请号：US13450907

申请日：2012-04-19

申请人： Thomas Kuenemund ,  Dennis Tischendorf ,  Uwe Weder

发明人： Thomas Kuenemund ,  Dennis Tischendorf ,  Uwe Weder

IPC分类号： H02H1/00 ,  H01L23/544 ,  H01L27/04

CPC分类号： H03K19/17768 ,  G06F21/755 ,  H01L21/761 ,  H01L23/544 ,  H01L23/573 ,  H01L27/04 ,  H01L27/1443 ,  H01L2924/0002 ,  H02H1/00 ,  H01L2924/00

摘要： A semiconductor component includes a semiconductor substrate, and a doped well having a well terminal and a transistor structure having at least one potential terminal formed in the semiconductor substrate. The transistor structure has a parasitic thyristor, and is at least partly arranged in the doped well. The potential terminal and the well terminal are connected via a resistor.

摘要翻译： 半导体部件包括半导体衬底，以及具有阱端子和晶体管结构的掺杂阱，其具有形成在半导体衬底中的至少一个电位端子。 晶体管结构具有寄生晶闸管，并且至少部分地布置在掺杂阱中。 电位端子和阱端子通过电阻连接。

公开(公告)号：US07916517B2

公开(公告)日：2011-03-29

申请号：US11561184

申请日：2006-11-17

申请人： Thomas Kuenemund

发明人： Thomas Kuenemund

IPC分类号： G11C11/00

CPC分类号： G06F21/75

摘要： A circuit arrangement having complementary data lines of a dual rail data bus, wherein in a regular operating phase the complementary data lines carry complementary signals, and in a precharge phase the complementary data lines assume an identical logic state or the same electrical potential. The circuit arrangement also has a device for detecting manipulation attempts, the device having a detector circuit, which outputs an alarm signal upon the occurrence of an identical logic state on both data lines in the regular operating phase.

摘要翻译： 具有双轨数据总线的互补数据线的电路装置，其中在常规工作阶段中，互补数据线承载互补信号，并且在预充电阶段，互补数据线呈现相同的逻辑状态或相同的电位。 电路装置还具有用于检测操作尝试的装置，该装置具有检测器电路，其在正常操作阶段中在两条数据线上发生相同逻辑状态时输出报警信号。

公开(公告)号：US07894242B2

公开(公告)日：2011-02-22

申请号：US12038393

申请日：2008-02-27

申请人： Thomas Kuenemund ,  Andreas Wenzel

发明人： Thomas Kuenemund ,  Andreas Wenzel

IPC分类号： G11C11/00

CPC分类号： G11C17/12 ,  G11C8/20 ,  G11C17/18

摘要： Device for storing a binary state defined by a first binary value and a second binary value complementary thereto, the device capable of being queried by a query signal so as to output, in dependence on a binary masking state, the first binary value at a first output and the second binary value at a second output or vice versa.

摘要翻译： 用于存储由第一二进制值和与其互补的第二二进制值定义的二进制状态的设备，所述设备能够被查询信号查询，以便根据二进制掩蔽状态来输出第一二进制值 输出，第二个二进制值在第二个输出，反之亦然。

公开(公告)号：US07707237B2

公开(公告)日：2010-04-27

申请号：US12184682

申请日：2008-08-01

申请人： Thomas Kuenemund

发明人： Thomas Kuenemund

IPC分类号： G06F7/52

CPC分类号： G06F7/506 ,  G06F2207/3896

摘要： A macrocell including an adder block with a plurality of bit-slice adders, a bypass path and a control unit adapted to receive a carry of a first neighboring macrocell, and to output a carry by generation within the adder block or by passage of the carry of the first neighboring macrocell through the bypass path to a second neighboring macrocell. The control unit is adapted to signal a validity of the carry output of the macrocell depending on a logical combination of states of the two carry output lines. The control unit is further adapted, depending on a validity signal of the first neighboring macrocell indicating a validity of the carry, to prevent forwarding the carry.

摘要翻译： 包括具有多个位片加法器的加法器块的宏单元，旁路路径和适于接收第一相邻宏单元的进位的控制单元，并且在加法器块内或通过进位输出输出进位 通过旁路路径到第二相邻宏小区。 控制单元适于根据两个进位输出线的状态的逻辑组合来发送宏小区的进位输出的有效性。 根据指示进位有效性的第一相邻宏单元的有效信号，控制单元进一步适用于防止转发进位。

公开(公告)号：US07468930B2

公开(公告)日：2008-12-23

申请号：US11686509

申请日：2007-03-15

申请人： Thomas Kuenemund

发明人： Thomas Kuenemund

IPC分类号： G11C5/14

CPC分类号： G11C11/419

摘要： The energy consumption of a static memory cell, which may be connected to a first bit line and a second bit line of a bit line pair by means of transistors, is reduced in an energy-saving mode of operation by adjusting the potentials on each of the bit lines of the bit line pair such that a potential difference between the gate terminals of the transistors and the bit lines of the bit line pair is reduced in comparison with a normal mode of operation.

摘要翻译： 可以通过晶体管连接到位线对的第一位线和第二位线的静态存储单元的能量消耗在节能的操作模式中通过调节每个 位线对的位线使得晶体管的栅极端子和位线对的位线之间的电位差与正常工作模式相比减小。

公开(公告)号：US20080071522A1

公开(公告)日：2008-03-20

申请号：US10572656

申请日：2006-03-20

申请人： Franz Klug ,  Thomas Kuenemund ,  Steffen Sonnekalb ,  Andreas Wenzel

发明人： Franz Klug ,  Thomas Kuenemund ,  Steffen Sonnekalb ,  Andreas Wenzel

IPC分类号： G10L19/02

CPC分类号： G06F11/08 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3879

摘要： A method for the protected transmission of data words involves provision of a first data word (X1), transformation of the first data word (X1) into a sequence comprising at least one second data word (X2) by a first transformation rule (T1), transformation of at least one of the second data words (X2) into a third data word (X3) by a second transformation rule (T2), and checking whether a prescribed relationship exists between the third data word (X3) and a comparison data word (VX).

摘要翻译： 用于数据字的受保护传输的方法涉及提供第一数据字（X 1），通过第一变换规则将第一数据字（X 1）转换成包括至少一个第二数据字（X 2）的序列 （T 1），通过第二变换规则（T 2）将至少一个第二数据字（X 2）转换成第三数据字（X 3），并且检查第三数据字之间是否存在规定的关系 （X 3）和比较数据字（VX）。

公开(公告)号：US20080040414A1

公开(公告)日：2008-02-14

申请号：US11890966

申请日：2007-08-08

申请人： Thomas Kuenemund

发明人： Thomas Kuenemund

IPC分类号： G06F7/38

CPC分类号： G06F7/5016 ,  G06F7/764

摘要： A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.

公开(公告)号：US08502585B2

公开(公告)日：2013-08-06

申请号：US13187772

申请日：2011-07-21

申请人： Thomas Kuenemund ,  Anton Huber ,  Roswitha Deppe

发明人： Thomas Kuenemund ,  Anton Huber ,  Roswitha Deppe

IPC分类号： H03K3/356

CPC分类号： H03K3/35625 ,  H03K3/356008 ,  H03K3/356156

摘要： A device includes a flip flop and a control circuit. The flip flop includes a flip flop data input terminal and a flip flop clock input terminal. The control circuit includes a control circuit data input terminal and a control circuit clock input terminal. The control circuit is configured to route, in a Data Processing Mode of the device, an incoming data signal from the control circuit data input terminal to the flip flop data input terminal and an incoming clock signal from the control circuit clock input terminal to the flip flop clock input terminal and to apply, in a Data Retention Mode of the device, a first given fixed signal value to the flip flop data input terminal independent of a value of the incoming data signal and a second given fixed signal value to the flip flop clock input terminal independent of a value of the incoming clock signal.

摘要翻译： 一种装置包括触发器和控制电路。 触发器包括触发器数据输入端和触发器时钟输入端。 控制电路包括控制电路数据输入端和控制电路时钟输入端。 控制电路被配置为在设备的数据处理模式中路由从控制电路数据输入端到触发器数据输入端的输入数据信号和从控制电路时钟输入端到触发器的输入时钟信号 并且在设备的数据保留模式中，将与输入数据信号的值无关的触发器数据输入端的第一给定固定信号值和向触发器的第二给定固定信号值应用于触发器时钟输入端 时钟输入端子独立于输入时钟信号的值。

公开(公告)号：US07826299B2

公开(公告)日：2010-11-02

申请号：US12106931

申请日：2008-04-21

申请人： Thomas Kuenemund ,  Artur Wroblewski

发明人： Thomas Kuenemund ,  Artur Wroblewski

IPC分类号： G11C8/00

CPC分类号： G11C7/1006 ,  G11C7/1009

摘要： A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask signal are used for all groups other than the selected group.

摘要翻译： 通过在使用逻辑无效掩码信号的情况下，仅为包括要访问的存储器单元的所选择的组提供逻辑有效的掩码信号来操作组中至少两组的每个组的多个屏蔽存储单元，每个组使用单独的屏蔽信号 对于所选组以外的所有组。