公开(公告)号：US5901307A

公开(公告)日：1999-05-04

申请号：US684720

申请日：1996-07-22

申请人： Terence Matthew Potter ,  Paul Charles Rossbach ,  Thomas Luther Thomas, Jr.

发明人： Terence Matthew Potter ,  Paul Charles Rossbach ,  Thomas Luther Thomas, Jr.

IPC分类号： G06F9/38 ,  G06F9/32

CPC分类号： G06F9/3848

摘要： A processor and method for speculatively executing a branch instruction are disclosed. The processor includes a branch prediction unit for predicting a resolution of a speculative branch instruction, which is selectively configurable such that resolution of the speculative branch instruction is predicted in response to only an address of the speculative branch instruction or in response to branch history of at least one previously executed branch instruction. The processor also includes an address calculation unit for determining a target address in response to the predicted resolution of the speculative branch instruction. In one embodiment, the processor further includes configuration logic for dynamically configuring the branch prediction logic.

摘要翻译： 公开了一种用于推测性地执行分支指令的处理器和方法。 该处理器包括：分支预测单元，用于预测推测分支指令的分辨率，该分支预测单元可选择性地配置，使得仅响应于推测分支指令的地址或响应于分支历史信号预测推测分支指令的分辨率 至少一个先前执行的分支指令。 处理器还包括用于响应于推测分支指令的预测分辨率来确定目标地址的地址计算单元。 在一个实施例中，处理器还包括用于动态配置分支预测逻辑的配置逻辑。

公开(公告)号：US5794024A

公开(公告)日：1998-08-11

申请号：US621552

申请日：1996-03-25

申请人： Robert Thaddeus Golla ,  Thomas Alan Hoy ,  Christopher Hans Olson ,  Terence Matthew Potter ,  Thomas Luther Thomas, Jr.

发明人： Robert Thaddeus Golla ,  Thomas Alan Hoy ,  Christopher Hans Olson ,  Terence Matthew Potter ,  Thomas Luther Thomas, Jr.

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3863 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： A method and system for dynamically recovering a lookahead register-address-table (RAT) in a processor that executes program instructions. Each instruction that updates a logical register address is assigned to a different physical register address. Each of the instructions to be processed by the processor are stored in a fifo queue. The physical register address assignments for each of the instructions are stored in a first RAT, and information regarding instructions that have completed execution by the processor are stored in a second RAT. The method and system further comprises storing the physical register address assignments for non-branch instructions from the fifo queue in a recovery RAT. The first RAT is then restored after an interrupt occurs by copying the second RAT into the recovery RAT and then copying the recovery RAT into the first RAT. The first RAT is restored after a mispredicted branch instruction has been executed by copying the recovery RAT into the first RAT, whereby the first RAT is restored without storing multiple snapshots.

摘要翻译： 一种用于在执行程序指令的处理器中动态地恢复前瞻寄存器地址表（RAT）的方法和系统。 将更新逻辑寄存器地址的每条指令分配给不同的物理寄存器地址。 要由处理器处理的每个指令都存储在一个fifo队列中。 每个指令的物理寄存器地址分配被存储在第一RAT中，并且关于处理器完成执行的指令的信息被存储在第二RAT中。 该方法和系统还包括将来自fifo队列的非分支指令的物理寄存器地址分配存储在恢复RAT中。 然后在通过将第二RAT复制到恢复RAT中然后将恢复RAT复制到第一RAT中来发生中断之后恢复第一RAT。 在通过将恢复RAT复制到第一RAT中执行错误预测的分支指令之后恢复第一RAT，由此在不存储多个快照的情况下恢复第一RAT。