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1.发明授权Method and system for dynamically recovering a register-address-table upon occurrence of an interrupt or branch misprediction 失效发生中断或分支错误预测时动态恢复寄存器地址表的方法和系统
公开(公告)号：US5794024A
公开(公告)日：1998-08-11
申请号：US621552
申请日：1996-03-25
申请人： Robert Thaddeus Golla , Thomas Alan Hoy , Christopher Hans Olson , Terence Matthew Potter , Thomas Luther Thomas, Jr.
发明人： Robert Thaddeus Golla , Thomas Alan Hoy , Christopher Hans Olson , Terence Matthew Potter , Thomas Luther Thomas, Jr.
CPC分类号： G06F9/3863 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A method and system for dynamically recovering a lookahead register-address-table (RAT) in a processor that executes program instructions. Each instruction that updates a logical register address is assigned to a different physical register address. Each of the instructions to be processed by the processor are stored in a fifo queue. The physical register address assignments for each of the instructions are stored in a first RAT, and information regarding instructions that have completed execution by the processor are stored in a second RAT. The method and system further comprises storing the physical register address assignments for non-branch instructions from the fifo queue in a recovery RAT. The first RAT is then restored after an interrupt occurs by copying the second RAT into the recovery RAT and then copying the recovery RAT into the first RAT. The first RAT is restored after a mispredicted branch instruction has been executed by copying the recovery RAT into the first RAT, whereby the first RAT is restored without storing multiple snapshots.
摘要翻译： 一种用于在执行程序指令的处理器中动态地恢复前瞻寄存器地址表（RAT）的方法和系统。 将更新逻辑寄存器地址的每条指令分配给不同的物理寄存器地址。 要由处理器处理的每个指令都存储在一个fifo队列中。 每个指令的物理寄存器地址分配被存储在第一RAT中，并且关于处理器完成执行的指令的信息被存储在第二RAT中。 该方法和系统还包括将来自fifo队列的非分支指令的物理寄存器地址分配存储在恢复RAT中。 然后在通过将第二RAT复制到恢复RAT中然后将恢复RAT复制到第一RAT中来发生中断之后恢复第一RAT。 在通过将恢复RAT复制到第一RAT中执行错误预测的分支指令之后恢复第一RAT，由此在不存储多个快照的情况下恢复第一RAT。
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公开(公告)号：US5880983A
公开(公告)日：1999-03-09
申请号：US620733
申请日：1996-03-25
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49942
摘要： A method and system for an infinite precision split multiply and add operation which has increased speed. The method and system for providing a split multiply and add of a plurality of operands include a multiplier and an adder means. The multiplier multiplies a first portion of the plurality of operands, thereby providing a product. The adder, which combines the remaining operands and the product, comprise at least one pair of data paths. Each pair of data paths comprises a first data path and a second data path. The first data path comprises a first aligner, a first adder, and a first normalizer capable of shifting a mantissa by a substantially fewer number digits than the aligner. The second data path comprises a second aligner, a second adder, and a second normalizer capable of shifting a mantissa by a substantially larger number of digits than the aligner. Accordingly, the present invention includes split multiply and add data paths which, individually, are faster than a fused multiply and add. In addition, the split multiply and add data paths can preserve the appearance of infinite precision. Consequently, overall system performance is increased.
摘要翻译： 一种用于无限精密分割乘法和加法运算的方法和系统，其具有增加的速度。 用于提供多个操作数的分割乘法和相加的方法和系统包括乘法器和加法器装置。 乘法器乘以多个操作数的第一部分，从而提供乘积。 组合剩余操作数和乘积的加法器包括至少一对数据路径。 每对数据路径包括第一数据路径和第二数据路径。 第一数据路径包括第一对准器，第一加法器和第一归一化器，其能够将尾数与对准器相比更少的数字位移。 第二数据路径包括第二对准器，第二加法器和第二归一化器，其能够将尾数移位比对准器大得多的位数。 因此，本发明包括分离的乘法和加法数据路径，其分别比融合乘法和加法更快。 此外，拆分乘法和添加数据路径可以保持无限精度的外观。 因此，整体系统性能提高。
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3.发明授权
公开(公告)号：US5790445A
公开(公告)日：1998-08-04
申请号：US641307
申请日：1996-04-30
摘要： A system and method for calculating a floating point add/subtract of a plurality of floating point operands is disclosed. The system comprises at least one pair of data paths. Each pair of data paths comprises a first data path and a second data path. The first data path includes a first aligner, a first adder coupled to the first aligner, and a first normalizer coupled to the first adder. The first normalizer is capable of shifting a mantissa by a substantially smaller number of digits than the first aligner. The second data path comprises control logic, a second aligner coupled to the control logic, a second adder coupled to the second aligner, and a second normalizer coupled to the second adder. The control logic provides a control signal that is responsive to a first predetermined number of digits of each exponent of a pair of exponents. The pair of exponents are the exponents for a pair of inputs to the second data path. The second aligner is responsive to the control signal provided by the control logic. In addition, the second normalizer is capable of shifting a mantissa by a substantially larger number of digits than the second aligner.
摘要翻译： 公开了一种用于计算多个浮点操作数的浮点加法/减法的系统和方法。 该系统包括至少一对数据路径。 每对数据路径包括第一数据路径和第二数据路径。 第一数据路径包括第一对准器，耦合到第一对准器的第一加法器和耦合到第一加法器的第一归一化器。 第一标准器能够将尾数移位比第一对准器小得多的位数。 第二数据路径包括控制逻辑，耦合到控制逻辑的第二对准器，耦合到第二对准器的第二加法器以及耦合到第二加法器的第二归一化器。 控制逻辑提供响应于一对指数的每个指数的第一预定数量位数的控制信号。 一对指数是对于第二数据路径的一对输入的指数。 第二对准器响应于由控制逻辑提供的控制信号。 此外，第二归一化器能够将尾数移动比第二对准器大得多的位数。
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4.发明授权Method and system for designing a circuit using RC and timing weighting of nets 失效使用RC设计电路的方法和系统以及网络的定时加权
公开(公告)号：US5815406A
公开(公告)日：1998-09-29
申请号：US620734
申请日：1996-03-25
CPC分类号： G06F17/5072
摘要： A timing driven placement system and method for designing an integrated circuit. The inventive method includes the steps of identifying a plurality of nets having blocks of circuit components connected by conductive elements and assigning weights to the nets in proportion to timing and resistive-capacitive (RC) effects therein. In the preferred embodiment, the weights are used by a conventional placement program to obtain the final placements.
摘要翻译： 一种用于设计集成电路的定时驱动放置系统和方法。 本发明的方法包括以下步骤：识别具有由导电元件连接的电路部件块并且与其中的定时和电阻 - 电容（RC）效应成比例地向网络分配权重的多个网。 在优选实施例中，权重由常规布置程序使用以获得最终布置。
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5.发明授权Method and system for processing multiple branch instructions that write to count and link registers 失效用于处理写入计数和链接寄存器的多个分支指令的方法和系统
公开(公告)号：US5943494A
公开(公告)日：1999-08-24
申请号：US486304
申请日：1995-06-07
CPC分类号： G06F9/30061 , G06F9/3842 , G06F9/3863
摘要： A system and method for processing count and link branch instructions that allows multiple branches to be outstanding at the same time without being limited to the number of rename registers allocated to the count and link registers. The method and system comprises an architected count register and an architected link register that are each connected to a look-ahead register. Information in the architected count or link register is copied into the look-ahead register when a branch instruction is encountered that will alter the contents of the count or link registers. Information in the look-ahead register is saved in a shadow register when an unresolved branch is encountered, and restored by the shadow register if the outcome of the unresolved branch is mispredicted.
摘要翻译： 用于处理计数和链接分支指令的系统和方法，其允许多个分支在同一时间未完成，而不限于分配给计数和链接寄存器的重命名寄存器的数量。 该方法和系统包括各自连接到预先注册的架构计数寄存器和架构的链接寄存器。 当遇到将改变计数或链接寄存器的内容的分支指令时，将结构计数或链接寄存器中的信息复制到预读寄存器中。 当遇到未解决的分支时，预览寄存器中的信息保存在影子寄存器中，如果未解析的分支的结果被错误预测，则由影子寄存器还原。
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6.发明授权Method and system for minimizing the delay in executing branch-on-register instructions 失效用于最小化执行分支指令指令的延迟的方法和系统
公开(公告)号：US5802346A
公开(公告)日：1998-09-01
申请号：US457714
申请日：1995-06-02
CPC分类号： G06F9/322 , G06F9/3824
摘要： A system and method for minimizing the delay associated with executing a register dependent instruction in which the execution of the register dependent instruction is dependent on an operand of a preceding instruction. In a branch unit for executing register dependent instructions, functional units are connected via a rename bus, and the functional units are connected to a general purpose register (GPR) via a GPR bus. The system and method routes the rename bus and the GPR bus directly to an instruction fetch address register thereby enabling the branch unit to execute a register dependent instruction during the same cycle as the preceding instruction.
摘要翻译： 一种用于最小化与执行依赖于寄存器的指令相关联的延迟的系统和方法，其中执行依赖于寄存器的指令取决于前一指令的操作数。 在用于执行与寄存器有关的指令的分支单元中，功能单元经由重命名总线连接，功能单元通过GPR总线连接到通用寄存器（GPR）。 系统和方法将重命名总线和GPR总线直接传送到指令获取地址寄存器，从而使分支单元在与前一指令相同的周期内执行与寄存器相关的指令。
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7.发明授权Method and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processors 失效用于执行上下文改变指令而不在高性能处理器内执行上下文同步操作的方法和系统
公开(公告)号：US5898864A
公开(公告)日：1999-04-27
申请号：US918059
申请日：1997-08-25
CPC分类号： G06F9/3863 , G06F9/3842
摘要： A method and system for executing a context-altering instruction within a processor are disclosed. The processor has a superscalar architecture that includes multiple pipelines, buffers, registers, and execution units. The processor also includes a machine state register for identifying a context of the processor, and a shadow machine state register in conjunction with the machine state register. During operation, a first state of the machine state register is copied to the shadow machine state register. Instructions are executed in accordance with a context identified by the first state of the machine state register. The first state of the shadow machine state register is subsequently altered to a second state in response to decoding a context-altering instruction. The context-altering instruction and subsequent instructions are then executed in accordance with the second state of the shadow machine state register. Finally, the first state of the machine state register is altered to the second state in response to a completion of the context-altering instruction. As a result context synchronization operations are avoided.
摘要翻译： 公开了一种用于在处理器内执行上下文更改指令的方法和系统。 处理器具有超标量架构，其包括多个管道，缓冲器，寄存器和执行单元。 处理器还包括用于识别处理器的上下文的机器状态寄存器和与机器状态寄存器一起的影子机状态寄存器。 在运行期间，机器状态寄存器的第一个状态被复制到影子机状态寄存器。 根据由机器状态寄存器的第一状态识别的上下文来执行指令。 响应于解码上下文改变指令，影子机状态寄存器的第一状态随后被改变到第二状态。 然后根据影子机状态寄存器的第二状态执行上下文改变指令和随后的指令。 最后，响应于上下文改变指令的完成，机器状态寄存器的第一状态被改变到第二状态。 因此，避免了上下文同步操作。
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