摘要:
In connection with a host processing system (90) capable of delivering commands and raw image data, an apparatus (100) for formatting raw image data and selectively delivering enhanced image data to a print processing subsystem (92). An image data bus section (120) comprises an image bus interface (122) coupled to a host processing system (90) configured to transmit raw image data, a front end memory (124) coupled to the image bus interface (122) to receive the raw image data, a back end memory (126) for receiving the enhanced image data, and a print processing subsystem (92) coupled to the back end memory (126) via a print interface (128) for transmitting print data based on the enhanced image data. A processor bus section (140) comprises an image processor (146) and a processor bus interface (142) adapted to be coupled to the host processing system (90) in order to communicate print processing instructions between the print processor (146) and the computer (90). A gateway (160) couples the print processor (146) to the front end memory (124) and the back end memory (126) whereby the print processor (146) receives the raw image data from the front end memory (124), formats the image data, and transmits the enhanced image data to the back end memory (126). The image data signals and the processor instruction signals are separated and transmitted over separate buses and bus interfaces to minimize processor I/O wait states and parasitic capacitance.
摘要:
A method and apparatus for transmitting data to a printhead by moving a carriage while the printhead records on a receiver medium. The printhead includes a plurality of recording elements and first electronic circuitry is also mounted with the printhead on the carriage for bi-directional movement with the carriage. An optical data link is coupled to the first electronic circuitry. The optical data link carries image data signals from second electronic circuitry remote from the carriage. A multiplexer multiplexes image data signals for transmission to the optical data link. The first electronic circuitry on the carriage includes a demultiplexer that demultiplexes the image data into signals for operation of the printhead.
摘要:
An inkjet printhead assembly (50) for an inkjet printer having a printhead (10) with a plurality of nozzles (24) and data path and control electronics circuitry (56) operably coupled with the printhead (10) for providing image data that control the flow of ink through the nozzles (24). The nozzles (24) are arranged in sections with actuators (28a, 28b) predisposed about each nozzle (24), for causing the nozzles (24) to print. Interconnections (54) between the data path and control electronics circuitry (56) and printhead (10) include DATA, CLOCK, LATCH and ENABLE lines which are used to operate the printhead (10) and, in turn, the nozzles (24) via shift register stages (228). The actuators (28a, 28b) are supported by the shift register stages (228) into which data is shifted from register stage to register stage for loading data that enables the actuators (28a, 28b). The shift registers stages (228) for all actuators (28a, 28b) are located to one side of the print head (10) to facilitate cleaning of the nozzles (24).
摘要:
An image processor (14) supporting very high-speed printing. The image processor (14) preferably has two separate connections to a source (12) of the image being printed, e.g., a printer control bus (34) and an image data bus (36). The image processor (14) preferably accepts images from the image source (12) in commonly known graphics file formats, such as the well-known 24-bit, uncompressed TIFF file format. The image processor (14) is a multiprocessor implementation. Preferably, one processor (30) coordinates or “orchestrates” control of the printing system and handshaking with the image source via the printer control bus (34) and the other processor (32) functions as a raster image processor (RIP) processor (52) and accepts and stores images into the printer environment from the image source (12) via the image data bus (36). The RIP processor (52) preferably performs color separation on the image into color planes and transmits each color plane to a separate processing path from that point on in the imaging chain. Each color plane preferably has a separate imaging path out from a shared image data bus (62). This separate path for each color plane preferably includes a band manager (54), a print engine or nozzle controller (60), and a print head (58).
摘要:
An apparatus for offset lithographic printing including an offset lithographic printing press including a printing cylinder having a surface including a mixture of cationic colloidal silica, fumed alumina, and a polymeric amine; and an inkjet printhead disposed to print a digital image on the printing cylinder with an ink jet fluid including a pigment and a polymeric dispersing agent, which ink jet fluid dries to produce a surface active to oleophilic lithographic printing inks.
摘要:
A system for automatically associating user-generated data to images, the system comprises a card reading device which receives and recognizes the user-generated data entered directly from manipulation of the terminal by a user. A camera captures an image and receives the data from the card reader device for associating a captured image and the data for forming a labeled image.
摘要:
A method for preparing lithographic printing plates comprising coating a substrate with a mixture including colloidal silica, fumed alumina, polyethylenimine, a quaternary ammonium polymer and a hardener; utilizing an inkjet printer with pigmented inks to print a digital image on the coated substrate; and drying the image.
摘要:
An inkjet printhead assembly (50) for an inkjet printer having a printhead (10) with a plurality of nozzles (24) and data path and control electronics circuitry (56) operably coupled with the printhead (10) for providing image data that control the flow of ink through the nozzles (24). The nozzles (24) are arranged in sections with at least two heater elements, an upper heater (28a) and a lower heater (28b), predisposed about each nozzle (24), the heater elements configured to actuate a nozzle (24) for printing. The data path and control electronics circuitry (56) comprises a plurality of shift registers (100, 102) configured to drive the nozzles, causing them to deliver ink in the direction of a receiver media, such as paper. Interconnections (54) between the data path and control electronics circuitry (56) and printhead (10) include DATA, CLOCK, LATCH and ENABLE lines which are used to operate the printhead (10) and, in turn, the nozzles (24) via the shift register stages (100, 102). The number of interconnections are minimized by interleaving data to the shift registers between upper and lower heater elements of the printhead (10) or by interleaving the data on the DATA line to the shift register stages (104, 106) for the upper and lower heater elements.
摘要:
An apparatus (100) for formatting bitmapped image data for printing. An image data bus section (120) has an image bus interface (122) adapted to be coupled to a computer bus to transmit the image data, a front end memory (124) coupled to the image bus interface (122) to receive the image data in an unformatted form, a back end memory (126) for receiving the image data in a formatted form, and a print interface device (1280 coupled to the back end memory (126) for transmitting print data based on the image data in a formatted form. A processor bus section (140) has an image processor (146) and a processor bus interface (1420 adapted to be coupled to the computer bus to communicate print processing instructions between the print processor (146) and the computer. A gateway (160) couples the print processor (146) to the front end memory (124) and the back end memory (126) whereby the print processor 9146) receives the image data in an unformatted form from the front end memory (124), formats the image data, and transmits the image data in a formatted form to the back end memory (126). The image data signals and the processor instruction signals are separated and transmitted over separate buses and bus interfaces to minimize processor I/O wait states and parasitic capacitance.