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    Method and apparatus for floating point operations and format conversion operations
    1.
    发明授权
    Method and apparatus for floating point operations and format conversion operations 有权
    用于浮点运算和格式转换操作的方法和装置

    公开(公告)号：US07216138B2

    公开(公告)日：2007-05-08

    申请号：US09783875

    申请日：2001-02-14

    Applicant: Mohammad Abdallah ,  Prasad Modali ,  Chien-Yu Huang, legal representative ,  Thomas R. Huff ,  Vladimir Pentkovski ,  Patrice Roussel ,  Shreekant S. Thakkar

    Inventor： Hsien-Cheng E. Hsieh, deceased

    IPC: G06F7/00 ,  G06F9/30

    CPC classification number: H03M7/24

    Abstract: A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format.Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. One or more numbers in the floating point format are converted to the integer format and placed in a register of a second set of architectural registers in a packed format. Conversion from integer format to floating point format is performed in a similar manner.A floating point arithmetic apparatus is described that provides for converting a plurality of numbers between integer formats and a floating point formats, further providing for conversion operations that require a greater data path width than floating-point arithmetic operations.

    Abstract translation: 描述了一种方法和装置，用于响应于控制信号格式的控制信号将数字从浮点格式转换为整数格式或从整数格式转换为浮点格式。 数字以浮点格式存储在打包格式的第一组结构寄存器的寄存器中。 浮点格式中的一个或多个数字被转换为整数格式，并以打包格式放置在第二组体系结构寄存器的寄存器中。 以类似的方式执行从整数格式到浮点格式的转换。 描述了一种浮点运算装置，其提供了整数格式和浮点格式之间的多个数字的转换，进一步提供了需要比浮点算术运算更大的数据路径宽度的转换操作。

    System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields
    5.
    发明授权
    System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields 有权
    用于减少处理器中使用包括操作类代码和操作选择器代码字段的指令格式所需的操作码数量的系统

    公开(公告)号：US06185670B2

    公开(公告)日：2001-02-06

    申请号：US09170136

    申请日：1998-10-12

    Applicant: Thomas R. Huff ,  Shreekant S. Thakkar ,  Roger A. Golliver

    Inventor： Thomas R. Huff ,  Shreekant S. Thakkar ,  Roger A. Golliver

    IPC: G06F1500

    CPC classification number: G06F9/30032 ,  G06F9/30021 ,  G06F9/30145 ,  G06F9/30167

    Abstract: A method and apparatus for reducing the number of opcodes required in a computer architecture using an operation class code and an operation selector code. A processor contains a fetch unit which fetches instructions to be executed by the processor. An instruction may conform to an instruction format which includes a number of fields that specify an operation class code, an operation selector code, and one or more operands. The processor also contains a decoder which uses the operation class code to generate a single execution flow that is capable of executing a class of similar operations. The single execution flow, in the form of execution control information, is sent to an execution unit along with the associated operands. The operation selector code is also passed to the execution unit. The execution unit performs the specific operation identified by the operation selector code and execution control information.

    Abstract translation: 一种用于减少使用操作类代码和操作选择器代码的计算机体系结构中所需的操作码数量的方法和装置。 一个处理器包含一个提取单元，它提取要由处理器执行的指令。 指令可以符合包括指定操作类代码，操作选择器代码和一个或多个操作数的多个字段的指令格式。 该处理器还包含一个解码器，它使用操作类代码来生成能够执行类似操作类的单个执行流。 执行控制信息形式的单个执行流程与关联的操作数一起发送到执行单元。 操作选择器代码也被传递给执行单元。 执行单元执行由操作选择器代码和执行控制信息识别的特定操作。

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