公开(公告)号：US09940134B2

公开(公告)日：2018-04-10

申请号：US13475708

申请日：2012-05-18

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F9/3005 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/5005 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4068

Abstract: A method for decentralized resource allocation in an integrated circuit. The method includes receiving a plurality of requests from a plurality of resource consumers of a plurality of partitionable engines to access a plurality resources, wherein the resources are spread across the plurality of engines and are accessed via a global interconnect structure. At each resource, a number of requests for access to said each resource are added. At said each resource, the number of requests are compared against a threshold limiter. At said each resource, a subsequent request that is received that exceeds the threshold limiter is canceled. Subsequently, requests that are not canceled within a current clock cycle are implemented.

公开(公告)号：US09733942B2

公开(公告)日：2017-08-15

申请号：US13360024

申请日：2012-01-27

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30174 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30098 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/45516 ,  G06F12/0875 ,  G06F15/8007 ,  G06F2212/452

Abstract: A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling guest instructions into a guest instruction block; and conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The hardware further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, and a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block, wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache.

公开(公告)号：US09710399B2

公开(公告)日：2017-07-18

申请号：US13561491

申请日：2012-07-30

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/12 ,  G06F12/126 ,  G06F12/0802

CPC classification number: G06F12/128 ,  G06F12/0802 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/126 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/70

Abstract: Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.

公开(公告)号：US09430410B2

公开(公告)日：2016-08-30

申请号：US13561528

申请日：2012-07-30

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08 ,  G06F12/14

CPC classification number: G06F12/1458 ,  G06F12/0846 ,  G06F12/0897 ,  G06F2212/1052 ,  G06F2212/221 ,  G06F2212/62

Abstract: A method for supporting a plurality of load accesses is disclosed. A plurality of requests to access a data cache is accessed, and in response, a tag memory is accessed that maintains a plurality of copies of tags for each entry in the data cache. Tags are identified that correspond to individual requests. The data cache is accessed based on the tags that correspond to the individual requests. A plurality of requests to access the same block of the plurality of blocks causes an access arbitration that is executed in the same clock cycle as is the access of the tag memory.

Abstract translation: 公开了一种用于支持多个负载访问的方法。 访问多个访问数据高速缓存的请求，并且作为响应，访问维护数据高速缓存中的每个条目的标签的多个副本的标签存储器。 识别符合个别请求的标签。 基于与各个请求对应的标签访问数据高速缓存。 多个访问多个块的相同块的请求导致在与标签存储器的访问相同的时钟周期中执行的访问仲裁。

公开(公告)号：US20140189311A1

公开(公告)日：2014-07-03

申请号：US13732243

申请日：2012-12-31

Applicant: Patrice Roussel ,  Srinivas Chennupaty ,  Michael Cranford ,  Mohammad Abdallah ,  James Coke ,  Katherine Kong

Inventor： Patrice Roussel ,  Srinivas Chennupaty ,  Michael Cranford ,  Mohammad Abdallah ,  James Coke ,  Katherine Kong

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032

Abstract: An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.

Abstract translation: 描述了使用计算机实现的步骤对打包数据执行洗牌操作的装置和方法。 在一个实施例中，访问具有至少两个数据元素的第一打包数据操作数。 具有至少两个数据元素的第二压缩数据操作数被访问。 第一打包数据操作数中的数据元素之一被混洗到目的地寄存器的较低目的地字段中，并且第二打包数据操作数中的数据元素中的一个被混洗到目的地寄存器的上目的地字段中。

公开(公告)号：US20140032845A1

公开(公告)日：2014-01-30

申请号：US13561528

申请日：2012-07-30

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08

CPC classification number: G06F12/1458 ,  G06F12/0846 ,  G06F12/0897 ,  G06F2212/1052 ,  G06F2212/221 ,  G06F2212/62

Abstract: A method for supporting a plurality of load accesses is disclosed. A plurality of requests to access a data cache is accessed, and in response, a tag memory is accessed that maintains a plurality of copies of tags for each entry in the data cache. Tags are identified that correspond to individual requests. The data cache is accessed based on the tags that correspond to the individual requests. A plurality of requests to access the same block of the plurality of blocks causes an access arbitration that is executed in the same clock cycle as is the access of the tag memory.

Abstract translation: 公开了一种用于支持多个负载访问的方法。 访问多个访问数据高速缓存的请求，并且作为响应，访问维护数据高速缓存中的每个条目的多个标签副本的标签存储器。 识别符合个别请求的标签。 基于与各个请求对应的标签访问数据高速缓存。 多个访问多个块的相同块的请求导致在与标签存储器的访问相同的时钟周期中执行的访问仲裁。

公开(公告)号：US20130238874A1

公开(公告)日：2013-09-12

申请号：US13414456

申请日：2012-03-07

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/0802 ,  G06F12/0875 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/608 ,  G06F2212/651 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.

公开(公告)号：US20130024619A1

公开(公告)日：2013-01-24

申请号：US13359961

申请日：2012-01-27

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F12/08

CPC classification number: G06F9/30174 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/3808 ,  G06F9/3836 ,  G06F9/3863 ,  G06F9/4552 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method for translating instructions for a processor. The method includes accessing a guest instruction and performing a first level translation of the guest instruction using a first level conversion table. The method further includes outputting a resulting native instruction when the first level translation proceeds to completion. A second level translation of the guest instruction is performed using a second level conversion table when the first level translation does not proceed to completion, wherein the second level translation further processes the guest instruction based upon a partial translation from the first level conversion table. The resulting native instruction is output when the second level translation proceeds to completion.

Abstract translation: 一种用于翻译处理器的指令的方法。 该方法包括访问客户指令并使用第一级转换表执行访客指令的第一级转换。 该方法还包括当第一级转换进行到完成时输出结果本地指令。 当第一级转换不进行到完成时，使用第二级转换表执行访客指令的第二级转换，其中第二级转换还基于来自第一级转换表的部分转换进一步处理客户指令。 当第二级转换进行到完成时，输出所产生的本机指令。

公开(公告)号：US20120246450A1

公开(公告)日：2012-09-27

申请号：US13428438

申请日：2012-03-23

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/30

CPC classification number: G06F9/5077 ,  G06F9/30043 ,  G06F9/30123 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/5016 ,  G06F9/505 ,  G06F12/0848 ,  G06F13/1657 ,  G06F2212/282

Abstract: A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality register file segments are coupled to the partitionable engines for providing data storage.

Abstract translation: 一种用于使用用于处理器的多个寄存器文件段来执行指令的系统。 该系统包括用于接收输入指令序列的全局前端调度器，其中全局前端调度器将输入指令序列划分为指令的多个代码块，并且生成描述代码块指令之间相互依赖关系的多个继承向量。 该系统还包括处理器的多个虚拟核心，其耦合以接收由全局前端调度器分配的代码块，其中每个虚拟核心包括多个可分区引擎的相应资源子集，其中通过使用 根据虚拟核心模式并根据各自的继承向量的可分割引擎。 多个寄存器文件段被耦合到可分割引擎以提供数据存储。

公开(公告)号：US20120198168A1

公开(公告)日：2012-08-02

申请号：US13359939

申请日：2012-01-27

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F9/30174 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/4552 ,  G06F12/0864 ,  G06F12/0891 ,  G06F2212/151 ,  G06F2212/452

Abstract: A method for managing a variable caching structure for managing storage for a processor. The method includes using a multi-way tag array to store a plurality of pointers for a corresponding plurality of different size groups of physical storage of a storage stack, wherein the pointers indicate guest addresses that have corresponding converted native addresses stored within the storage stack, and allocating a group of storage blocks of the storage stack, wherein the size of the allocation is in accordance with a corresponding size of one of the plurality of different size groups. Upon a hit on the tag, a corresponding entry is accessed to retrieve a pointer that indicates where in the storage stack a corresponding group of storage blocks of converted native instructions reside. The converted native instructions are then fetched from the storage stack for execution.

Abstract translation: 一种用于管理用于管理处理器的存储的可变高速缓存结构的方法。 该方法包括使用多路标签阵列来存储用于存储堆栈的相应多个不同大小的物理存储组的多个指针，其中指针指示存储在存储堆栈中的相应转换的本地地址的客户地址， 以及分配所述存储堆栈的一组存储块，其中所述分配的大小根据所述多个不同大小组中的一个的相应大小。 在标签上点击时，访问相应的条目以检索指示器，该指针指示存储堆栈中转换的本地指令的相应组的存储块的位置。 然后从存储堆栈中获取转换后的本机指令以便执行。