公开(公告)号：US20070165346A1

公开(公告)日：2007-07-19

申请号：US11712938

申请日：2007-03-02

申请人： Wee Lee ,  Tu Yun ,  Tian Teo

发明人： Wee Lee ,  Tu Yun ,  Tian Teo

IPC分类号： H02H3/20

CPC分类号： H01L27/0251 ,  H04L25/08

摘要： A circuit for protection of a transceiver input includes an input transistor and a first resistor connected between the drain of the input transistor and an input node. A plurality of reverse-biased diodes connected between a supply voltage and the input node. An output node is connected to the source of the input transistor. A first forward-biased diode connected between the power supply and the plurality of reverse-biased transistors. A second forward-biased diode and a second resistor are connected between the first forward biased transistor and the gate of the input transistor. A pre-driver circuit includes first and second transistors forming a differential pair and driven by a differential input voltage. A third transistor is connected between sources of the first and second transistors and ground. First and second resistors are connected to drains of the first and second transistors, respectively. A fourth transistor is connected between a power supply voltage and the first and second resistors. Fifth and a sixth transistors are connected in series between the power supply voltage and the first and second resistors, wherein a node between the fifth and second transistors is connected to a gate of the fourth transistor.

摘要翻译： 用于保护收发器输入的电路包括输入晶体管和连接在输入晶体管的漏极和输入节点之间的第一电阻器。 连接在电源电压和输入节点之间的多个反向偏置二极管。 输出节点连接到输入晶体管的源极。 连接在电源和多个反向偏置晶体管之间的第一正向偏置二极管。 第二正向偏置二极管和第二电阻连接在第一正向偏置晶体管和输入晶体管的栅极之间。 预驱动器电路包括形成差分对并由差分输入电压驱动的第一和第二晶体管。 第三晶体管连接在第一和第二晶体管的源极和地之间。 第一和第二电阻分别连接到第一和第二晶体管的漏极。 第四晶体管连接在电源电压和第一和第二电阻之间。 第五和第六晶体管串联在电源电压和第一和第二电阻之间，其中第五和第二晶体管之间的节点连接到第四晶体管的栅极。

公开(公告)号：US20050190516A1

公开(公告)日：2005-09-01

申请号：US10787937

申请日：2004-02-27

申请人： Wee Lee ,  Tu Yun ,  Tian Teo

发明人： Wee Lee ,  Tu Yun ,  Tian Teo

IPC分类号： H01L27/02 ,  H02H3/20 ,  H04L25/08

CPC分类号： H01L27/0251 ,  H04L25/08

摘要： A circuit for protection of a transceiver input includes an input transistor and a first resistor connected between the drain of the input transistor and an input node. A plurality of reverse-biased diodes connected between a supply voltage and the input node. An output node is connected to the source of the input transistor. A first forward-biased diode connected between the power supply and the plurality of reverse-biased transistors. A second forward-biased diode and a second resistor are connected between the first forward biased transistor and the gate of the input transistor. A pre-driver circuit includes first and second transistors forming a differential pair and driven by a differential input voltage. A third transistor is connected between sources of the first and second transistors and ground. First and second resistors are connected to drains of the first and second transistors, respectively. A fourth transistor is connected between a power supply voltage and the first and second resistors. Fifth and a sixth transistors are connected in series between the power supply voltage and the first and second resistors, wherein a node between the fifth and second transistors is connected to a gate of the fourth transistor.

摘要翻译： 用于保护收发器输入的电路包括输入晶体管和连接在输入晶体管的漏极和输入节点之间的第一电阻器。 连接在电源电压和输入节点之间的多个反向偏置二极管。 输出节点连接到输入晶体管的源极。 连接在电源和多个反向偏置晶体管之间的第一正向偏置二极管。 第二正向偏置二极管和第二电阻连接在第一正向偏置晶体管和输入晶体管的栅极之间。 预驱动器电路包括形成差分对并由差分输入电压驱动的第一和第二晶体管。 第三晶体管连接在第一和第二晶体管的源极和地之间。 第一和第二电阻分别连接到第一和第二晶体管的漏极。 第四晶体管连接在电源电压和第一和第二电阻之间。 第五和第六晶体管串联在电源电压和第一和第二电阻之间，其中第五和第二晶体管之间的节点连接到第四晶体管的栅极。

公开(公告)号：US20060076993A1

公开(公告)日：2006-04-13

申请号：US10961201

申请日：2004-10-12

申请人： Tian Teo ,  David Ho

发明人： Tian Teo ,  David Ho

IPC分类号： H04N5/91 ,  H03K5/01 ,  H04N5/93

CPC分类号： H03L7/107 ,  H03K5/13 ,  H03K2005/00052 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0337

摘要： A clock and data recovery system for detecting and resolving meta-stability conditions is provided. The clock and data recovery system includes a phase detector having logic configured to detect a meta-stability condition and to generate an output signal to mitigate the condition. The system can also include a time varying gain adjustment portion. This portion includes a gain control logic configured to determine and adjust system gain during reception of an incoming data stream. The system further includes a phase interpolator having increased linearity. The phase interpolator has a plurality of first branches having a differential transistor pair, a switch, and a current source, coupled between a first output and a first supply voltage and a plurality of second branches having a differential transistor pair, a switch, and a current source, coupled between a second output and the first supply voltage. The phase interpolator can also include an integrator portion.

摘要翻译： 提供了一种用于检测和解决元稳定性条件的时钟和数据恢复系统。 时钟和数据恢复系统包括具有逻辑的相位检测器，该逻辑被配置为检测元稳定性条件并产生输出信号以减轻条件。 该系统还可以包括时变增益调整部分。 该部分包括被配置为在接收输入数据流期间确定和调整系统增益的增益控制逻辑。 该系统还包括具有增加的线性度的相位插值器。 相位插值器具有多个第一分支，其具有耦合在第一输出和第一电源电压之间的差分晶体管对，开关和电流源，以及具有差分晶体管对，开关和 电流源，耦合在第二输出和第一电源电压之间。 相位插值器还可以包括积分器部分。