公开(公告)号：US07650542B2

公开(公告)日：2010-01-19

申请号：US11013586

申请日：2004-12-16

申请人： James Douglas Sweet ,  Tianwen Tang

发明人： James Douglas Sweet ,  Tianwen Tang

IPC分类号： G01R31/28 ,  G11C29/00 ,  G01R31/26

CPC分类号： G01R31/31705 ,  G01R31/318555 ,  G01R31/318558 ,  G06F11/267

摘要： Aspects of a method and system of using a single EJTAG interface for multiple TAP controllers may comprise communicating information to a plurality of debugging interfaces, the method comprising simultaneously broadcasting a single debug message to a plurality of TAP controllers where the debug message is received via a single debug interface. The method may further comprise simultaneously broadcasting the single debug message to selected ones of a plurality of TAP controllers. An input enable register control signal may be generated that selects which, of a plurality of TAP controllers, is to receive the debug message. The single debug interface may be a JTAG interface which is capable of receiving and sending JTAG messages, or EJTAG messages.

摘要翻译： 对于多个TAP控制器使用单个EJTAG接口的方法和系统的方面可以包括将信息传送到多个调试接口，所述方法包括同时向多个TAP控制器广播单个调试消息，其中经由 单调试接口。 该方法还可以包括同时向多个TAP控制器中的选定的调试消息广播单个调试消息。 可以生成输入使能寄存器控制信号，其选择多个TAP控制器中的哪一个接收调试消息。 单个调试接口可以是能够接收和发送JTAG消息或EJTAG消息的JTAG接口。

公开(公告)号：US20080155490A1

公开(公告)日：2008-06-26

申请号：US11615270

申请日：2006-12-22

申请人： Tianwen Tang ,  Raghunath Vutukuru ,  Chao-Cheng Yeh

发明人： Tianwen Tang ,  Raghunath Vutukuru ,  Chao-Cheng Yeh

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5077

摘要： Methods for reducing coupling noise, reducing signal skew, and saving layout area for an integrated circuit. Aspects of one method may include prioritizing a plurality of clock signals for layout on a chip. The clock signals may comprise functional and test clock signals and test clock signals, where the functional and test clock signals may not both be active at the same time. The clock signals may be routed based on the prioritization, where the priority may be based on, for example, frequency and/or slew rate of each clock signal. A route guide may also be used to take into account an amount of cross-talk reduction desired for each clock signal and/or whether a metal layer may be used may also be used in routing the clock signals. The clocks signals may also be routed so that the functional clock signals may be interlaced with the test clock signals.

摘要翻译： 降低耦合噪声，降低信号偏移，节省集成电路布局面积的方法。 一种方法的方面可以包括对芯片上布局的多个时钟信号进行优先级排序。 时钟信号可以包括功能和测试时钟信号和测试时钟信号，其中功能和测试时钟信号可能不能同时被激活。 可以基于优先级来路由时钟信号，其中优先级可以基于例如每个时钟信号的频率和/或转换速率。 还可以使用路线指南来考虑每个时钟信号所需的串扰减少量和/或是否可以使用金属层也可用于路由时钟信号。 时钟信号也可以被路由使得功能时钟信号可以与测试时钟信号隔行扫描。

公开(公告)号：US20060156099A1

公开(公告)日：2006-07-13

申请号：US11013586

申请日：2004-12-16

申请人： James Sweet ,  Tianwen Tang

发明人： James Sweet ,  Tianwen Tang

IPC分类号： G01R31/28

CPC分类号： G01R31/31705 ,  G01R31/318555 ,  G01R31/318558 ,  G06F11/267

摘要： Aspects of a method and system of using a single EJTAG interface for multiple TAP controllers may comprise communicating information to a plurality of debugging interfaces, the method comprising simultaneously broadcasting a single debug message to a plurality of TAP controllers where the debug message is received via a single debug interface. The method may further comprise simultaneously broadcasting the single debug message to selected ones of a plurality of TAP controllers. An input enable register control signal may be generated that selects which, of a plurality of TAP controllers, is to receive the debug message. The single debug interface may be a JTAG interface which is capable of receiving and sending JTAG messages, or EJTAG messages.

摘要翻译： 对于多个TAP控制器使用单个EJTAG接口的方法和系统的方面可以包括将信息传送到多个调试接口，所述方法包括同时向多个TAP控制器广播单个调试消息，其中经由 单调试接口。 该方法还可以包括同时向多个TAP控制器中的选定的调试消息广播单个调试消息。 可以生成输入使能寄存器控制信号，其选择多个TAP控制器中的哪一个接收调试消息。 单个调试接口可以是能够接收和发送JTAG消息或EJTAG消息的JTAG接口。