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公开(公告)号：US20090086533A1
公开(公告)日：2009-04-02
申请号：US12258682
申请日：2008-10-27
IPC分类号： G11C11/44
CPC分类号： G11C8/10 , Y10S505/831 , Y10S505/837
摘要： A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.
摘要翻译： 使用快速单通量量子（RSFQ）逻辑元件设计高速查找表，并使用超导集成电路制造。 查找表由地址解码器和可编程只读存储器阵列（PROM）组成。 存储器阵列具有快速的并行流水线读出和较慢的存储器内容的串行重新编程。 使用标准的非破坏性复位触发器（RSN单元）和数据触发器（DFF单元）构建存储单元。 n位地址解码器以相同的技术实现并与存储器阵列紧密集成，以实现作为查找表的高速操作。 电路架构可扩展到大型二维数据阵列。
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公开(公告)号：US07443719B2
公开(公告)日：2008-10-28
申请号：US11360749
申请日：2006-02-23
IPC分类号： G11C11/44
CPC分类号： G11C8/10 , Y10S505/831 , Y10S505/837
摘要： A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.
摘要翻译： 使用快速单通量量子（RSFQ）逻辑元件设计高速查找表，并使用超导集成电路制造。 查找表由地址解码器和可编程只读存储器阵列（PROM）组成。 存储器阵列具有快速的并行流水线读出和较慢的存储器内容的串行重新编程。 使用标准的非破坏性复位触发器（RSN单元）和数据触发器（DFF单元）构建存储单元。 n位地址解码器以相同的技术实现并与存储器阵列紧密集成，以实现作为查找表的高速操作。 电路架构可扩展到大型二维数据阵列。
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公开(公告)号：US20110167241A1
公开(公告)日：2011-07-07
申请号：US13043272
申请日：2011-03-08
CPC分类号： G11C8/10 , Y10S505/831 , Y10S505/837
摘要： A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.
摘要翻译： 使用快速单通量量子（RSFQ）逻辑元件设计高速查找表，并使用超导集成电路制造。 查找表由地址解码器和可编程只读存储器阵列（PROM）组成。 存储器阵列具有快速的并行流水线读出和较慢的存储器内容的串行重新编程。 使用标准的非破坏性复位触发器（RSN单元）和数据触发器（DFF单元）构建存储单元。 n位地址解码器以相同的技术实现并与存储器阵列紧密集成，以实现作为查找表的高速操作。 电路架构可扩展到大型二维数据阵列。
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公开(公告)号：US07991814B2
公开(公告)日：2011-08-02
申请号：US11895478
申请日：2007-08-24
CPC分类号： H01L39/045 , H01L39/025 , H01L39/2493 , H03K5/13 , H03K2005/00286 , H05K13/0469
摘要： The invention includes a novel differentiator cell, a novel resample unit cell, and precision synchronization circuitry to ensure proper timing of the circuits and systems at the anticipated ultra-high speed of operation. The novel differentiator cell includes circuitry for combining a carry input signal, a data bit signal and the output signal of a NOT cell and applying the signals as distinct and separate pulses to the input of a toggle flip-flop (TFF) for producing an asynchronous carry output and a clocked data output. The novel differentiator cells can be interconnected to form a multi-bit differentiator circuit using appropriate delay and synchronization circuitry to compensate for delays in producing the carry output of each cell which is applied to a succeeding cell. The novel resample cell includes a non-destructive reset-set flip-flop (RSN) designed to receive a data bit, at its set input, at a slow clock rate, which data is repeatedly read out of the RSN at a fast clock rate, until the RSN is reset. The novel differentiator and resampler cells can be interconnected, for example, to form the differentiator and up-sampling sections of a digital interpolation filter (DIF). Also, the relative clocking of bit slices (columns) in such a DIF may be achieved by using the fast clock signal to synchronize the slow clock which controls data entry. The circuits of the invention can be advantageously implemented with Josephson Junctions in rapid-single-flux-quantum (RSFQ) logic.
摘要翻译： 本发明包括一种新颖的微分单元，一种新的重采样单元，以及精确同步电路，用于确保在预期的超高速操作下电路和系统的正确定时。 新颖的微分器单元包括用于组合进位输入信号，数据位信号和NOT单元的输出信号的电路，并且将该信号作为截止触发器（TFF）的输入施加到截止触发器（TFF）的输入端，以产生异步 携带输出和时钟数据输出。 新颖的微分器单元可以互连以形成使用适当的延迟和同步电路的多位微分电路，以补偿产生应用于后续单元的每个单元的进位输出的延迟。 新型重采样单元包括一个非破坏性的复位触发器（RSN），它被设计为在其设定的输入处以慢的时钟速率接收一个数据位，该数据以快速时钟速率从RSN重复读出 ，直到RSN复位。 新颖的微分器和重采样器单元可以互连，例如形成数字插值滤波器（DIF）的微分器和上采样部分。 此外，这种DIF中的位片（列）的相对时钟可以通过使用快速时钟信号来同步控制数据输入的慢时钟来实现。 本发明的电路可以有利地用快速单通量 - 量子（RSFQ）逻辑中的约瑟夫逊接合来实现。
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公开(公告)号：US08401600B1
公开(公告)日：2013-03-19
申请号：US13196494
申请日：2011-08-02
CPC分类号： H03D7/005 , H01L39/025 , H01L39/223 , H04B1/0014
摘要： A superconducting multi-bit digital mixer, designed using rapid single flux quantum (RSFQ) logic, for multiplying two independent digital streams, at least one of these comprising a plurality of parallel bit lines, wherein the output is also a similar plurality of bit lines. In a preferred embodiment, one of the digital streams represents a local oscillator signal, and the other digital stream digital radio frequency input from an analog-to-digital converter. The multi-bit mixer comprises an array of bit-slices, with the local oscillator signal generated using shift registers. This multi-bit mixer is suitable for an integrated circuit with application to a broadband digital radio frequency receiver, a digital correlation receiver, or a digital radio frequency transmitter. A synchronous pulse distribution network is used to ensure proper operation at data rates of 20 GHz or above.
摘要翻译： 一种使用快速单通量量（RSFQ）逻辑设计的超导多位数字混频器，用于将两个独立数字流相乘，其中至少一个包括多个并行位线，其中该输出也是相似的多个位线 。 在优选实施例中，数字流中的一个表示本地振荡器信号，并且另一个数字流数字射频从模数转换器输入。 该多位混频器包括一个位片阵列，本地振荡器信号由移位寄存器产生。 该多位混频器适用于应用于宽带数字射频接收机，数字相关接收机或数字射频发射机的集成电路。 使用同步脉冲分配网络来确保在20 GHz或更高的数据速率下正常工作。
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公开(公告)号：US07903456B2
公开(公告)日：2011-03-08
申请号：US12258682
申请日：2008-10-27
IPC分类号： G11C11/44
CPC分类号： G11C8/10 , Y10S505/831 , Y10S505/837
摘要： A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.
摘要翻译： 使用快速单通量量子（RSFQ）逻辑元件设计高速查找表，并使用超导集成电路制造。 查找表由地址解码器和可编程只读存储器阵列（PROM）组成。 存储器阵列具有快速的并行流水线读出和较慢的存储器内容的串行重新编程。 使用标准的非破坏性复位触发器（RSN单元）和数据触发器（DFF单元）构建存储单元。 n位地址解码器以相同的技术实现并与存储器阵列紧密集成，以实现作为查找表的高速操作。 电路架构可扩展到大型二维数据阵列。
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公开(公告)号：US20080231353A1
公开(公告)日：2008-09-25
申请号：US11895478
申请日：2007-08-24
IPC分类号： H04B1/10
CPC分类号： H01L39/045 , H01L39/025 , H01L39/2493 , H03K5/13 , H03K2005/00286 , H05K13/0469
摘要： The invention includes a novel differentiator cell, a novel resample unit cell, and precision synchronization circuitry to ensure proper timing of the circuits and systems at the anticipated ultra-high speed of operation. The novel differentiator cell includes circuitry for combining a carry input signal, a data bit signal and the output signal of a NOT cell and applying the signals as distinct and separate pulses to the input of a toggle flip-flop (TFF) for producing an asynchronous carry output and a clocked data output. The novel differentiator cells can be interconnected to form a multi-bit differentiator circuit using appropriate delay and synchronization circuitry to compensate for delays in producing the carry output of each cell which is applied to a succeeding cell. The novel resample cell includes a non-destructive reset-set flip-flop (RSN) designed to receive a data bit, at its set input, at a slow clock rate, which data is repeatedly read out of the RSN at a fast clock rate, until the RSN is reset. The novel differentiator and resampler cells can be interconnected, for example, to form the differentiator and up-sampling sections of a digital interpolation filter (DIF). Also, the relative clocking of bit slices (columns) in such a DIF may be achieved by using the fast clock signal to synchronize the slow clock which controls data entry. The circuits of the invention can be advantageously implemented with Josephson Junctions in rapid-single-flux-quantum (RSFQ) logic.
摘要翻译： 本发明包括一种新颖的微分单元，一种新的重采样单元，以及精确同步电路，用于确保在预期的超高速操作下电路和系统的正确定时。 新颖的微分器单元包括用于组合进位输入信号，数据位信号和NOT单元的输出信号的电路，并且将该信号作为截止触发器（TFF）的输入施加到截止触发器（TFF）的输入端，以产生异步 携带输出和时钟数据输出。 新颖的微分器单元可以互连以形成使用适当的延迟和同步电路的多位微分电路，以补偿产生应用于后续单元的每个单元的进位输出的延迟。 新型重采样单元包括一个非破坏性的复位触发器（RSN），它被设计为在其设定的输入处以慢的时钟速率接收一个数据位，该数据以快速时钟速率从RSN重复读出 ，直到RSN复位。 新颖的微分器和重采样器单元可以互连，例如形成数字插值滤波器（DIF）的微分器和上采样部分。 此外，这种DIF中的位片（列）的相对时钟可以通过使用快速时钟信号来同步控制数据输入的慢时钟来实现。 本发明的电路可以有利地用快速单通量 - 量子（RSFQ）逻辑中的约瑟夫逊接合来实现。
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