Variable latency method and apparatus for floating-point coprocessor
    1.
    发明授权
    Variable latency method and apparatus for floating-point coprocessor 失效
    浮点协处理器的可变延迟方法和装置

    公开(公告)号:US5021985A

    公开(公告)日:1991-06-04

    申请号:US467879

    申请日:1990-01-19

    IPC分类号: G06F1/14 G06F7/00 G06F9/38

    摘要: A programmable latency (a programmable number of clock cycles) needed for an operation completion. The required latency for a pipe is determined from a formula including the system clock cycle time which the unit will be specified to operate under. The latency is preprogrammed by setting the count of a timer accordingly to provide at least the minimum number of clock cycles necessary to cover the time required to do the computation. Separate timers are independently set for arithmetic logic unit (ALU) operations, multiply operations, logical operations and divide and square root operations.

    摘要翻译: 操作完成所需的可编程延迟(可编程时钟周期数)。 管道所需的等待时间由包括系统时钟周期时间的公式确定,该单位将被指定在下面进行操作。 通过相应地设置定时器的计数来预编程等待时间,以提供至少需要的最小时钟周期数来覆盖进行计算所需的时间。 单独的定时器被独立地设置用于算术逻辑单元(ALU)操作,乘法运算,逻辑运算和除法和平方根运算。