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    Variable latency method and apparatus for floating-point coprocessor
    1.
    发明授权
    Variable latency method and apparatus for floating-point coprocessor 失效
    浮点协处理器的可变延迟方法和装置

    公开(公告)号：US5021985A

    公开(公告)日：1991-06-04

    申请号：US467879

    申请日：1990-01-19

    申请人： Larry Hu ,  Ting Chuk ,  John McLeod ,  Mark Birman ,  Allen Samuels ,  George K. Chu

    发明人： Larry Hu ,  Ting Chuk ,  John McLeod ,  Mark Birman ,  Allen Samuels ,  George K. Chu

    IPC分类号： G06F1/14 ,  G06F7/00 ,  G06F9/38

    CPC分类号： G06F9/3877 ,  G06F9/3836 ,  G06F9/3869

    摘要： A programmable latency (a programmable number of clock cycles) needed for an operation completion. The required latency for a pipe is determined from a formula including the system clock cycle time which the unit will be specified to operate under. The latency is preprogrammed by setting the count of a timer accordingly to provide at least the minimum number of clock cycles necessary to cover the time required to do the computation. Separate timers are independently set for arithmetic logic unit (ALU) operations, multiply operations, logical operations and divide and square root operations.

    摘要翻译： 操作完成所需的可编程延迟（可编程时钟周期数）。 管道所需的等待时间由包括系统时钟周期时间的公式确定，该单位将被指定在下面进行操作。 通过相应地设置定时器的计数来预编程等待时间，以提供至少需要的最小时钟周期数来覆盖进行计算所需的时间。 单独的定时器被独立地设置用于算术逻辑单元（ALU）操作，乘法运算，逻辑运算和除法和平方根运算。

    Apparatus for determining booth recoder input control signals
    3.
    发明授权
    Apparatus for determining booth recoder input control signals 失效
    用于确定展位编码器输入控制信号的装置

    公开(公告)号：US5280439A

    公开(公告)日：1994-01-18

    申请号：US774674

    申请日：1991-10-11

    申请人： S. M. Quek ,  Larry Hu ,  Jnyaneshwar P. Prabhu ,  Frederick A. Ware

    发明人： S. M. Quek ,  Larry Hu ,  Jnyaneshwar P. Prabhu ,  Frederick A. Ware

    IPC分类号： G06F7/52 ,  G06F7/552 ,  G06F17/11

    CPC分类号： G06F7/5338 ,  G06F17/11 ,  G06F7/535 ,  G06F7/552 ,  G06F7/5525 ,  G06F2207/382 ,  G06F2207/5355 ,  G06F2207/5356 ,  G06F2207/5521 ,  G06F2207/5523 ,  G06F7/4873 ,  G06F7/49957

    摘要： In an apparatus and method for computing inverses and square roots, a highly accurate initial approximation is computed using a second order polynomial equation, the coefficients of which are stored in a ROM. The most significant bits of an operand are used to address a ROM to select coefficients, providing different coefficients for different operand ranges. The remaining lesser significant operand bits are used in the computation; the coefficient values already account for the bits used to address them. The result is in single precision accuracy. For double precision, the polynomial results are used as the first approximation for a Newton-Raphson iteration. The multiplier has a split array mode to speed up the calculation of the polynomial, whereby two lesser precision values can be computed at once. The size of the coefficients is tailored to produce the proper precision result for each of the elements of Ax.sup.2 +Bx+C. Separate values for the coefficients A, B, and C must be stored for the 1/x approximation and for the 1/.sqroot.x approximation. Also to speed up the multiplier, the multiplier can accept one operand in carry/save format, by providing Booth recoder logic which can accept operands in a normal binary or in a carry/save format. Also employed is a rounding technique which provides IEEE exact rounding by an operation that includes only one multiplication.

    摘要翻译： 在用于计算反转和平方根的装置和方法中，使用二阶多项式方程来计算高精度的初始近似，其二次多项式方程存储在ROM中。 操作数的最高有效位用于寻址ROM以选择系数，为不同的操作数范围提供不同的系数。 其余较小的操作数位用于计算; 系数值已经是用于解决它们的位。 结果是单精度精度。 对于双精度，多项式结果被用作牛顿 - 拉夫逊迭代的第一近似。 乘法器具有分割阵列模式以加速多项式的计算，由此可以一次计算两个较小的精度值。 量化系数的大小，为Ax2 + Bx + C的每个元素产生适当的精度结果。 必须为1 / x近似和1 /（平方根）x近似存储系数A，B和C的单独值。 另外为了加快乘法器，乘法器可以通过提供可以以正常二进制或进位/保存格式接受操作数的Booth编码器逻辑，以进位/保存格式接受一个操作数。 同样采用的是舍入技术，其通过仅包括一个乘法的操作来提供IEEE精确舍入。

    Apparatus for multiplying operands
    6.
    发明授权
    Apparatus for multiplying operands 失效
    用于乘法运算的装置

    公开(公告)号：US5245564A

    公开(公告)日：1993-09-14

    申请号：US698758

    申请日：1991-05-10

    申请人： S. M. Quek ,  Larry Hu ,  Jnyaneshwar P. Prabhu ,  Frederick A. Ware

    发明人： S. M. Quek ,  Larry Hu ,  Jnyaneshwar P. Prabhu ,  Frederick A. Ware

    IPC分类号： G06F7/52 ,  G06F7/552 ,  G06F17/11

    CPC分类号： G06F7/5338 ,  G06F17/11 ,  G06F7/535 ,  G06F7/552 ,  G06F7/5525 ,  G06F2207/382 ,  G06F2207/5355 ,  G06F2207/5356 ,  G06F2207/5521 ,  G06F2207/5523 ,  G06F7/4873 ,  G06F7/49957

    摘要： In an apparatus and method for computing inverses and square roots a highly accurate initial approximation is computed using a second order polynomial equation, the coefficients of which are stored in a ROM. The most significant bits of an operand are used to address a ROM to select coefficients, providing different coefficients for different operand ranges. The remaining lesser significant operand bits are used in the computation; the coefficient values already account for the bits used to address them. The result is in single precision accuracy. For double precision, the polynomial results are used as the first approximation for a Newton-Raphson iteration. The multiplier has a split array mode to speed up the calculation of the polynomial, whereby two lesser precision values can be computed at once. The size of the coefficients is tailored to produce the proper precision result for each of the elements of Ax.sup.2 +Bx+C. Separate values for the coefficients A, B, and C must be stored for the 1/x approximation and for the 1/.sqroot.x approximation. Also to speed up the multiplier, the multiplier can accept one operand in carry/save format, by providing Booth recoder logic which can accept operands in a normal binary or in a carry/save format. Also employed is a rounding technique which provides IEEE exact rounding by an operation that includes only one multiplication.

    摘要翻译： 在用于计算反演和平方根的装置和方法中，使用二阶多项式方程来计算高精度的初始近似，其二次多项式方程被存储在ROM中。 操作数的最高有效位用于寻址ROM以选择系数，为不同的操作数范围提供不同的系数。 其余较小的操作数位用于计算; 系数值已经是用于解决它们的位。 结果是单精度精度。 对于双精度，多项式结果被用作牛顿 - 拉夫逊迭代的第一近似。 乘法器具有分割阵列模式以加速多项式的计算，由此可以一次计算两个较小的精度值。 量化系数的大小，为Ax2 + Bx + C的每个元素产生适当的精度结果。 必须为1 / x近似和1 / 2ROOT x近似存储系数A，B和C的单独值。 另外为了加快乘法器，乘法器可以通过提供可以以正常二进制或进位/保存格式接受操作数的Booth编码器逻辑，以进位/保存格式接受一个操作数。 同样采用的是舍入技术，其通过仅包括一个乘法的操作来提供IEEE精确舍入。