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公开(公告)号:US07245147B1
公开(公告)日:2007-07-17
申请号:US11119375
申请日:2005-04-29
申请人: Behzad Nouban , Toan D. Doan , Pooyan Khoshkoo
发明人: Behzad Nouban , Toan D. Doan , Pooyan Khoshkoo
IPC分类号: H03K19/173
CPC分类号: H03K19/1774 , H03K19/17744
摘要: The present invention provides circuitry for implementing a multiple data rate interface architectures for programmable logic devices. The programmable logic device of the invention includes a core and surrounding periphery. The core includes a plurality of logic elements arranged in an array. Some of the logic elements within the core include registers that are used as data registers for the multiple data rate interface.
摘要翻译: 本发明提供用于实现可编程逻辑器件的多数据速率接口架构的电路。 本发明的可编程逻辑器件包括一个核心和周围的周边。 核心包括以阵列布置的多个逻辑元件。 核心中的一些逻辑元件包括用作多数据速率接口的数据寄存器的寄存器。