公开(公告)号：US06735686B1

公开(公告)日：2004-05-11

申请号：US09608733

申请日：2000-06-30

申请人： Tohru Hiraoka ,  Tomonaga Itoi ,  Masashi Hakamada

发明人： Tohru Hiraoka ,  Tomonaga Itoi ,  Masashi Hakamada

IPC分类号： G06F938

CPC分类号： G06F9/3806 ,  G06F9/30145 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3842 ,  G06F9/3853 ,  G06F9/3867

摘要： According to the present invention, instruction decoding can be separated into two stages. In a first instruction decoding stage, multiple instructions are decoded in a single machine cycle. Also, in the first instruction decoding stage, when a branch instruction is decoded a memory is requested to read a branch destination instruction for the branch instruction. The instructions decoded in the first instruction decoding stage is stored temporarily in instruction flow registers. In a second instruction decoding stage, instructions read sequentially from the instruction flow registers are decoded.

摘要翻译： 根据本发明，指令解码可分为两个阶段。 在第一指令解码级中，多个指令在单个机器周期中被解码。 此外，在第一指令解码级中，当分支指令被解码时，请求存储器读取分支指令的分支目的地指令。 在第一指令解码级中解码的指令被临时存储在指令流寄存器中。 在第二指令解码级中，从指令流寄存器顺序读取的指令被解码。

公开(公告)号：US5490259A

公开(公告)日：1996-02-06

申请号：US93969

申请日：1993-07-21

申请人： Tohru Hiraoka ,  Hiromichi Kainoh ,  Akira Yamaoka

发明人： Tohru Hiraoka ,  Hiromichi Kainoh ,  Akira Yamaoka

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1027

摘要： Under such a condition between outputs of AND circuits for outputting All "0" when one of zero detecting circuits of two register identifiers within an instruction register detects "0", instead of a content of a general-purpose register designated by these identifiers, and also a carry derived from a page offset corresponding to an intermediate result of an address adder, when a page address portion of a logical address is known before this logical address is defined, selecting circuits are controlled, and then the address controller is bypassed to retrieve a translation look-aside buffer, thereby defining a real address. In case that the page address portion of the logical address register is identical to the page address portion of the base register, the translation look-aside buffer is previously retrieved in accordance with either the content of the index register, or the content of the base register so that the real address can be defined.

摘要翻译： 在指令寄存器内的两个寄存器标识符的零检测电路之一检测到“0”时，用于输出全“0”的AND电路的输出之间的这种条件，而不是由这些标识符指定的通用寄存器的内容，以及 也是从与地址加法器的中间结果相对应的页偏移得到的进位，当在定义该逻辑地址之前逻辑地址的页地址部分已知时，选择电路被控制，然后旁路地址控制器以检索 翻译后备缓冲区，从而定义一个实际地址。 在逻辑地址寄存器的页地址部分与基址寄存器的页地址部分相同的情况下，根据索引寄存器的内容或基址的内容预先检索翻译后备缓冲器 注册，以便可以定义实际地址。