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公开(公告)号：US20080141074A1
公开(公告)日：2008-06-12
申请号：US11976544
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： G06F11/00
CPC分类号： H04L1/0045 , G06F11/10 , H04L1/0063 , H04L1/243 , H04L1/244
摘要： An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
摘要翻译： 错误检测器具有产生从CPU I / F向存储器发送的数据串的错误检测数据的奇偶校验位产生器，基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器，以及 选择器电路，其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。 当选择器电路被切换以从CPU输出数据时，基于从选择器电路输出的错误检测数据，误差检测器进行包括奇偶位产生器和奇偶校验器中的至少一个的错误检测功能的故障诊断 。
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公开(公告)号：US08027352B2
公开(公告)日：2011-09-27
申请号：US11976546
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/66
CPC分类号： H04L47/10 , H04L12/40026 , H04L12/4625 , H04L43/106 , H04L47/283 , H04L47/31 , H04L47/32 , H04L49/206 , H04L49/30 , H04L49/351 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
摘要翻译： 用于在多个不同的通信信道之间执行帧数据的传送控制的网关装置设置有用于将时间戳信息添加到接收到的帧数据的时间戳单元和用于确定帧数据的处理延迟或异常的数据丢弃单元 通过参考时间戳信息和删除在发送帧数据时添加到帧数据的时间戳信息的装置。
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公开(公告)号：US08122316B2
公开(公告)日：2012-02-21
申请号：US11976544
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
CPC分类号： H04L1/0045 , G06F11/10 , H04L1/0063 , H04L1/243 , H04L1/244
摘要： An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
摘要翻译： 错误检测器具有产生从CPU I / F向存储器发送的数据串的错误检测数据的奇偶校验位产生器，基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器，以及 选择器电路，其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。 当选择器电路被切换以从CPU输出数据时，基于从选择器电路输出的错误检测数据，误差检测器进行包括奇偶位产生器和奇偶校验器中的至少一个的错误检测功能的故障诊断 。
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公开(公告)号：US20080101393A1
公开(公告)日：2008-05-01
申请号：US11976546
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/66
CPC分类号： H04L47/10 , H04L12/40026 , H04L12/4625 , H04L43/106 , H04L47/283 , H04L47/31 , H04L47/32 , H04L49/206 , H04L49/30 , H04L49/351 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
摘要翻译： 用于在多个不同的通信信道之间执行帧数据的传送控制的网关装置设置有用于将时间戳信息添加到接收的帧数据的时间戳单元和用于确定帧数据的处理延迟或异常的数据丢弃单元 通过参考时间戳信息和删除在发送帧数据时添加到帧数据的时间戳信息的装置。
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公开(公告)号：US08265087B2
公开(公告)日：2012-09-11
申请号：US11976687
申请日：2007-10-26
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/28
CPC分类号： H04L12/66 , H04L12/4135 , H04L12/4625 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
摘要翻译： 用于在通信信道之间执行帧数据的传输控制的网关装置包括存储关于帧数据的ID信息和关于使用该ID信息的通信信道的信息的路由图，以及将帧数据路由到传送的搜索引擎单元 基于接收的帧数据的ID信息和路由图。 当接收到的帧数据的ID信息是在接收帧数据的通信信道中未使用的ID信息时，搜索引擎单元不将帧数据传送到传送目的地。
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公开(公告)号：US20080101394A1
公开(公告)日：2008-05-01
申请号：US11976687
申请日：2007-10-26
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/28
CPC分类号： H04L12/66 , H04L12/4135 , H04L12/4625 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
摘要翻译： 用于在通信信道之间执行帧数据的传输控制的网关装置包括存储关于帧数据的ID信息和关于使用该ID信息的通信信道的信息的路由图，以及将帧数据路由到传送的搜索引擎单元 基于接收的帧数据的ID信息和路由图。 当接收到的帧数据的ID信息是在接收帧数据的通信信道中未使用的ID信息时，搜索引擎单元不将帧数据传送到传送目的地。
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