公开(公告)号：US09106352B2

公开(公告)日：2015-08-11

申请号：US13405529

申请日：2012-02-27

申请人： Qun Zheng ,  Thomas Geyer ,  Tonghua Zhang

发明人： Qun Zheng ,  Thomas Geyer ,  Tonghua Zhang

IPC分类号： G06F15/16 ,  H04J3/06

CPC分类号： H04J3/0641 ,  H04J3/0658 ,  H04J3/0667

摘要： A data network node is configured for operation as a time-transfer boundary clock, and has at least one time-transfer slave network interface and several time-transfer master interfaces, all configured for operation according to a time-transfer protocol. The data network node also includes a clock source interface configured for connection to a synchronous clock source supplied from a remote node, as well as a real-time clock (RTC) circuit. The RTC circuit supplies time-of-day data for time-transfer messages sent via the second network port and selectively operates in a first mode, wherein the RTC frequency is driven by a clock signal from the clock source interface, a second mode, wherein the RTC frequency is driven by a clock signal derived from time-transfer messages received by the time-transfer slave interface, and a third mode, wherein the RTC frequency is driven by a local clock signal from local clock source.

摘要翻译： 数据网络节点被配置为作为时间传输边界时钟进行操作，并且具有至少一个时间转移从网络接口和多个时间传输主接口，所有这些都被配置为根据时间传输协议进行操作。 数据网络节点还包括配置用于连接到从远程节点提供的同步时钟源以及实时时钟（RTC）电路的时钟源接口。 RTC电路为通过第二网络端口发送的时间传送消息提供时间数据，并且选择性地以第一模式操作，其中RTC频率由来自时钟源接口的时钟信号驱动，第二模式，其中 RTC频率由时间传输从接口接收的时间传递消息导出的时钟信号驱动，第三模式，其中RTC频率由本地时钟源的本地时钟信号驱动。

公开(公告)号：US20130279525A1

公开(公告)日：2013-10-24

申请号：US13452653

申请日：2012-04-20

申请人： Qun Zheng ,  Thomas Geyer ,  Tonghua Zhang

发明人： Qun Zheng ,  Thomas Geyer ,  Tonghua Zhang

IPC分类号： H04J3/06

CPC分类号： H04J3/0667

摘要： Clock phase errors are detected and adjusted in a network with loop back connections for clock signals. In one embodiment, a method is performed in a ring network with slave clock nodes. A timing packet is sent from the master clock node to a first slave clock node of the ring. A timing packet is received from a last slave clock node of the ring. A phase alignment offset is determined by comparing a recovered time from the received timing packet with the time of the master clock node local clock and a phase correction value is determined for the slave clock nodes based on the determined phase alignment offset. A phase correction packet including the phase correction value is then sent from the master clock node to at least one of the slave clock nodes.

摘要翻译： 在具有时钟信号的环回连接的网络中检测和调整时钟相位误差。 在一个实施例中，在具有从时钟节点的环形网络中执行一种方法。 定时分组从主时钟节点发送到环的第一从时钟节点。 从环的最后一个从时钟节点接收定时分组。 通过将来自接收的定时分组的恢复时间与主时钟节点本地时钟的时间进行比较来确定相位对准偏移，并且基于所确定的相位对准偏移，为从时钟节点确定相位校正值。 然后将包括相位校正值的相位校正分组从主时钟节点发送到至少一个从时钟节点。

公开(公告)号：US20130227172A1

公开(公告)日：2013-08-29

申请号：US13405529

申请日：2012-02-27

申请人： Qun Zheng ,  Thomas Geyer ,  Tonghua Zhang

发明人： Qun Zheng ,  Thomas Geyer ,  Tonghua Zhang

IPC分类号： G06F15/16

CPC分类号： H04J3/0641 ,  H04J3/0658 ,  H04J3/0667

摘要： A data network node is configured for operation as a time-transfer boundary clock, and has at least one time-transfer slave network interface and several time-transfer master interfaces, all configured for operation according to a time-transfer protocol. The data network node also includes a clock source interface configured for connection to a synchronous clock source supplied from a remote node, as well as a real-time clock (RTC) circuit. The RTC circuit supplies time-of-day data for time-transfer messages sent via the second network port and selectively operates in a first mode, wherein the RTC frequency is driven by a clock signal from the clock source interface, a second mode, wherein the RTC frequency is driven by a clock signal derived from time-transfer messages received by the time-transfer slave interface, and a third mode, wherein the RTC frequency is driven by a local clock signal from local clock source.

摘要翻译： 数据网络节点被配置为作为时间传输边界时钟进行操作，并且具有至少一个时间转移从网络接口和多个时间传输主接口，所有这些都被配置为根据时间传输协议进行操作。 数据网络节点还包括配置用于连接到从远程节点提供的同步时钟源以及实时时钟（RTC）电路的时钟源接口。 RTC电路为通过第二网络端口发送的时间传送消息提供时间数据，并且选择性地以第一模式操作，其中RTC频率由来自时钟源接口的时钟信号驱动，第二模式，其中 RTC频率由时间传输从接口接收的时间传递消息导出的时钟信号驱动，第三模式，其中RTC频率由本地时钟源的本地时钟信号驱动。

公开(公告)号：US08995473B2

公开(公告)日：2015-03-31

申请号：US13452653

申请日：2012-04-20

申请人： Qun Zheng ,  Thomas Geyer ,  Tonghua Zhang

发明人： Qun Zheng ,  Thomas Geyer ,  Tonghua Zhang

IPC分类号： H04J3/06

CPC分类号： H04J3/0667

摘要： Clock phase errors are detected and adjusted in a network with loop back connections for clock signals. In one embodiment, a method is performed in a ring network with slave clock nodes. A timing packet is sent from the master clock node to a first slave clock node of the ring. A timing packet is received from a last slave clock node of the ring. A phase alignment offset is determined by comparing a recovered time from the received timing packet with the time of the master clock node local clock and a phase correction value is determined for the slave clock nodes based on the determined phase alignment offset. A phase correction packet including the phase correction value is then sent from the master clock node to at least one of the slave clock nodes.

摘要翻译： 在具有时钟信号的环回连接的网络中检测和调整时钟相位误差。 在一个实施例中，在具有从时钟节点的环形网络中执行一种方法。 定时分组从主时钟节点发送到环的第一从时钟节点。 从环的最后一个从时钟节点接收定时分组。 通过将来自接收的定时分组的恢复时间与主时钟节点本地时钟的时间进行比较来确定相位对准偏移，并且基于所确定的相位对准偏移，为从时钟节点确定相位校正值。 然后将包括相位校正值的相位校正分组从主时钟节点发送到至少一个从时钟节点。