公开(公告)号：US5107137A

公开(公告)日：1992-04-21

申请号：US576940

申请日：1990-09-04

申请人： Masanori Kinugasa ,  Munenobu Kida ,  Toshimasa Ishikawa

发明人： Masanori Kinugasa ,  Munenobu Kida ,  Toshimasa Ishikawa

IPC分类号： H03K3/037 ,  H03K3/356 ,  H03K3/3562 ,  H03K3/3565

CPC分类号： H03K3/35625 ,  H03K3/0372 ,  H03K3/3565

摘要： In a master-slave type flip-flop circuit comprising a master output holding circuit of the master stage circuit, the threshold value of the input circuit of the slave stage circuit has a hysteresis characteristic in which the high level threshold value is set to a higher value than the threshold value of the master output holding circuit and the low level threshold value is set to a lower value than the threshold value of the master output holding circuit. Due to the feature, a phenomenon is prevented in which the output is once inverted and then again inverted in the metastable state.