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公开(公告)号：US5990541A
公开(公告)日：1999-11-23
申请号：US432521
申请日：1995-05-01
申请人： Satoshi Saito , Toyohiro Harazono
发明人： Satoshi Saito , Toyohiro Harazono
IPC分类号： H01L21/3205 , H01L21/316 , H01L21/318 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , H01L2924/0002
摘要： A semiconductor device comprising: a silicon nitride film formed on a semiconductor substrate having a first wiring layer; a first silicon oxide film formed on said silicon nitride film; and a second silicon oxide film formed on said first silicon oxide film by way of an atmospheric pressure CVD process using tetraethyl orthosilicate, siloxane, or disilazane as a source material.
摘要翻译： 一种半导体器件，包括：形成在具有第一布线层的半导体衬底上的氮化硅膜; 形成在所述氮化硅膜上的第一氧化硅膜; 以及通过使用原硅酸四乙酯，硅氧烷或二硅氮烷作为源材料的大气压CVD法在所述第一氧化硅膜上形成的第二氧化硅膜。
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公开(公告)号：US20110042730A1
公开(公告)日：2011-02-24
申请号：US12805675
申请日：2010-08-12
IPC分类号： H01L29/772 , H01L21/762
CPC分类号： H01L21/76224 , H01L29/78
摘要： A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, an liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
摘要翻译： 提供了可以形成具有优异特性的高压晶体管的元件隔离膜的形成方法。 在基板上预先形成栅极氧化膜。 在其上形成CMP阻挡膜，然后蚀刻栅极氧化膜和CMP阻挡膜。 蚀刻半导体衬底以形成沟槽。 此外，在沟槽填充有场绝缘膜之前，在沟槽内壁形成衬垫绝缘膜，在CMP阻挡膜下方的栅极氧化膜的侧面的凹部填充有衬垫绝缘膜 。 以这种方式，可以防止在相对于栅极氧化膜横向定位的元件隔离膜中形成空隙。
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公开(公告)号：US08482074B2
公开(公告)日：2013-07-09
申请号：US13137599
申请日：2011-08-29
IPC分类号： H01L29/78
CPC分类号： H01L21/76224 , H01L29/78
摘要： A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, a liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
摘要翻译： 提供了可以形成具有优异特性的高压晶体管的元件隔离膜的形成方法。 在基板上预先形成栅极氧化膜。 在其上形成CMP阻挡膜，然后蚀刻栅极氧化膜和CMP阻挡膜。 蚀刻半导体衬底以形成沟槽。 此外，在沟槽填充有场绝缘膜之前，在沟槽内壁形成有衬垫绝缘膜，在CMP阻挡膜下方的栅极氧化膜的侧面的凹部填充有衬垫绝缘膜 。 以这种方式，可以防止在相对于栅极氧化膜横向定位的元件隔离膜中形成空隙。
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公开(公告)号：US20120139052A1
公开(公告)日：2012-06-07
申请号：US13137599
申请日：2011-08-29
IPC分类号： H01L29/06
CPC分类号： H01L21/76224 , H01L29/78
摘要： A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, a liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
摘要翻译： 提供了可以形成具有优异特性的高压晶体管的元件隔离膜的形成方法。 在基板上预先形成栅极氧化膜。 在其上形成CMP阻挡膜，然后蚀刻栅极氧化膜和CMP阻挡膜。 蚀刻半导体衬底以形成沟槽。 此外，在沟槽填充有场绝缘膜之前，在沟槽内壁形成有衬垫绝缘膜，在CMP阻挡膜下方的栅极氧化膜的侧面的凹部填充有衬垫绝缘膜 。 以这种方式，可以防止在相对于栅极氧化膜横向定位的元件隔离膜中形成空隙。
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公开(公告)号：US08105894B2
公开(公告)日：2012-01-31
申请号：US12805675
申请日：2010-08-12
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L29/78
摘要： A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, an liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
摘要翻译： 提供了可以形成具有优异特性的高压晶体管的元件隔离膜的形成方法。 在基板上预先形成栅极氧化膜。 在其上形成CMP阻挡膜，然后蚀刻栅极氧化膜和CMP阻挡膜。 蚀刻半导体衬底以形成沟槽。 此外，在沟槽填充有场绝缘膜之前，在沟槽内壁形成衬垫绝缘膜，在CMP阻挡膜下方的栅极氧化膜的侧面的凹部填充有衬垫绝缘膜 。 以这种方式，可以防止在相对于栅极氧化膜横向定位的元件隔离膜中形成空隙。
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