公开(公告)号：US5663892A

公开(公告)日：1997-09-02

申请号：US412503

申请日：1995-03-29

申请人： Sachio Hayashi ,  Tyusei Ogawa

发明人： Sachio Hayashi ,  Tyusei Ogawa

IPC分类号： H01L21/822 ,  G06F17/50 ,  H01L21/82 ,  H01L27/04

CPC分类号： G06F17/5081

摘要： A method for performing compaction of a layout of a semiconductor integrated circuit designed in a hierarchy is described. The compaction of the layout is carried out by repeating a single level compaction process for compacting cell layouts in one of the hierarchical levels from a lowest level to a highest level of the hierarchical levels. The single level compaction process comprises a first replacement step of replacing lower level cell layouts in a current level cell layout with abstract cell layouts having the same profile and the same positions of terminals to be connected to the current level cell layout as the lower level cell layouts have in advance of compaction. The compaction of the current level cell is performed under a constraint that the relocations of the terminals of the current level cell layout after compaction from the original positions before compaction are possible within prescribed ranges. After compaction, the abstract cell layouts is replaced by the lower level cell layouts.

摘要翻译： 描述了一种用于执行层次化设计的半导体集成电路的布局压缩的方法。 布局的压缩是通过重复单层压缩过程来实现的，从而将层次级别中的一个层级中的单层布局压缩成层级级别的最低级别。 单级压缩处理包括第一替换步骤，用当前级单元布局替换下一级单元格布局，其中抽象单元格布局具有与下一层单元相同的轮廓和要连接到当前级单元布局的相同位置的终端 布局在压实之前。 在压缩之前的当前级别单元布局的端子从压实前的原始位置的重定位在规定范围内可能的约束下执行当前级单元的压缩。 压缩后，抽象单元格布局被较低级别的单元格布局所替代。