公开(公告)号：US09105728B2

公开(公告)日：2015-08-11

申请号：US13557039

申请日：2012-07-24

申请人： John Hyunchul Hong ,  Cheonhong Kim ,  Tze-Ching Fung

发明人： John Hyunchul Hong ,  Cheonhong Kim ,  Tze-Ching Fung

IPC分类号： H01L29/76 ,  H01L29/786

CPC分类号： H01L29/78645 ,  H01L29/78648

摘要： This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and configured to receive first, second, and third control signals, respectively. Dielectric layers insulate the gates from the semiconducting layer and from one another. In a first mode, the first, second, and third gates are configured such that charge is stored in a potential well in a region of the semiconducting layer adjacent the second gate. In a second mode, the first, second and third gate electrodes are configured such that the stored charge is transferred through the region of the semiconducting layer adjacent the third gate electrode and through the source to a load.

摘要翻译： 本公开提供了多栅极晶体管，结构，器件，器件，系统和相关工艺的实现。 一方面，一种器件包括布置在衬底上的薄膜半导体层。 漏极和源极耦合到半导体层。 该器件还包括第一，第二和第三栅极，其全部布置成邻近半导体层并被配置为分别接收第一，第二和第三控制信号。 电介质层将栅极与半导体层和彼此绝缘。 在第一模式中，第一，第二和第三栅极被配置为使得电荷存储在邻近第二栅极的半导体层的区域中的势阱中。 在第二模式中，第一，第二和第三栅电极被配置为使得存储的电荷通过与第三栅电极相邻的半导体层的区域并通过源传输到负载。

公开(公告)号：US20140027758A1

公开(公告)日：2014-01-30

申请号：US13557039

申请日：2012-07-24

申请人： John Hyunchul Hong ,  Cheonhong Kim ,  Tze-Ching Fung

发明人： John Hyunchul Hong ,  Cheonhong Kim ,  Tze-Ching Fung

IPC分类号： H01L29/22 ,  H01L29/786

CPC分类号： H01L29/78645 ,  H01L29/78648

摘要： This disclosure provides implementations of multi-gate transistors, structures, devices, apparatus, systems, and related processes. In one aspect, a device includes a thin-film semiconducting layer arranged over a substrate. A drain and source are coupled to the semiconducting layer. The device also includes first, second and third gates all arranged adjacent the semiconducting layer and configured to receive first, second, and third control signals, respectively. Dielectric layers insulate the gates from the semiconducting layer and from one another. In a first mode, the first, second, and third gates are configured such that charge is stored in a potential well in a region of the semiconducting layer adjacent the second gate. In a second mode, the first, second and third gate electrodes are configured such that the stored charge is transferred through the region of the semiconducting layer adjacent the third gate electrode and through the source to a load.

摘要翻译： 本公开提供了多栅极晶体管，结构，器件，器件，系统和相关工艺的实现。 一方面，一种器件包括布置在衬底上的薄膜半导体层。 漏极和源极耦合到半导体层。 该器件还包括第一，第二和第三栅极，其全部布置成邻近半导体层并被配置为分别接收第一，第二和第三控制信号。 电介质层将栅极与半导体层和彼此绝缘。 在第一模式中，第一，第二和第三栅极被配置为使得电荷存储在邻近第二栅极的半导体层的区域中的势阱中。 在第二模式中，第一，第二和第三栅电极被配置为使得存储的电荷通过邻近第三栅电极的半导体层的区域并且通过源传输到负载。