Decision network for receiver of PSK digital signals
    1.
    发明授权
    Decision network for receiver of PSK digital signals 失效
    PSK数字信号接收机的决策网络

    公开(公告)号:US4076956A

    公开(公告)日:1978-02-28

    申请号:US670534

    申请日:1976-03-25

    IPC分类号: H04L27/38 H04L15/24

    CPC分类号: H04L27/38

    摘要: In a phase-shift-keying (PSK) signaling system with or without amplitude modulation, using two channel carriers of like frequency in relative phase quadrature to identify one of eight signal levels, each signal level is associated with one of eight equispaced radii emanating from the center of an orthogonal matrix or coordinate system. That matrix is divided by its coordinate axes into four quadrants each encompassing three zones of potential signal deviation, i.e. a middle zone centered on the bisector of the quadrant and two lateral zones whose outer boundaries coincide with those of the quadrant. The signals incoming at a receiver input over the two channels are coherently detected and filtered to supply a pair of coordinates defining a point on the matrix generally falling into one of the three zones of a quadrant; upon conversion into digital form, with six modular bits and one sign bit each, these signals by their modular bits address one of 4,096 cells of a first read-only memory to call forth one of three two-bit combinations stored in these cells. The bit combination so read out identifies the zone -- irrespective of quadrant -- defined by the detected coordinates; these bits, together with the sign bits derived from the incoming signals, address one of 12 cells in a second read-only memory which thereupon delivers a three-bit word indicating the corresponding signal level and, if desired, two collateral multibit words fed back to the receiver input for correcting distortions of the next-following signals.

    摘要翻译: 在具有或不具有幅度调制的相移键控(PSK)信令系统中,使用相对相位正交中相似频率的两个信道载波来识别八个信号电平中的一个,每个信号电平与从八分之一发出的八个等间隔半径中的一个相关联 正交矩阵或坐标系的中心。 该矩阵被其坐标轴划分成四个象限,每个象限围绕着三个区域的潜在信号偏差,即以象限的二等分线为中心的中间区域和两个外边界与象限的外边界重合。 在两个通道上的接收机输入端输入的信号被相干地检测和滤波,以提供一对坐标,该坐标定义在矩阵上的点通常落入象限的三个区域之一中; 在转换成数字形式时,每个具有六个模块位和一个符号位,这些信号通过它们的模块位址寻址第一只读存储器的4096个单元之一,以调用存储在这些单元中的三个两位组合之一。 所读取的位组合识别区域 - 无论由检测到的坐标定义的象限如何; 这些位与从输入信号导出的符号位一起寻址在第二只读存储器中的12个单元之一,随后传送指示对应的信号电平的三位字,并且如果需要,反馈两个副载波多位字 到接收机输入端,用于校正下一个跟随信号的失真。

    Adaptive correction of phase errors in noncoherent demodulation of
carrier asymmetrically modulated with digital signals
    2.
    发明授权
    Adaptive correction of phase errors in noncoherent demodulation of carrier asymmetrically modulated with digital signals 失效
    自适应校正不正确的数字信号调制载波的相位误差的自适应校正

    公开(公告)号:US4048572A

    公开(公告)日:1977-09-13

    申请号:US752168

    申请日:1976-12-20

    IPC分类号: H04L27/06 H03K9/04

    CPC分类号: H04L27/066

    摘要: Digital signals asymmetrically modulated upon a carrier, with suppressed or vestigial second sideband, are recovered at a receiver by pseudo-coherent demodulation or periodic sampling and subsequent digitization to provide a train of raw data signals X from which a train of raw quadrature signals Y is derived by digital filtration. Signals X and Y are fed to a phase corrector where they are cross-multiplied with a sine function and a cosine function of a feedback signal W, approximating a corrective phase angle .phi.(t), to yield a corrected in-phase signal X' and a corrected quadrature signal Y'. Signal X' is quantized to provide a reference signal c which, upon subtraction from signal X', produces a bipolar difference signal whose sign bit is multiplied with either the entire signal Y' or its sign bit to provide an error signal V. The latter is averaged over a number of clock cycles, resulting in the feedback signal W whose trigonometric functions are read out from a memory for utilization in the generation of corrected signals X' and Y'.

    Digital demodulator with interpolation for linearly amplitude-modulated
data signals
    3.
    发明授权
    Digital demodulator with interpolation for linearly amplitude-modulated data signals 失效
    具有线性幅度调制数据信号插值的数字解调器

    公开(公告)号:US4121165A

    公开(公告)日:1978-10-17

    申请号:US790081

    申请日:1977-04-22

    IPC分类号: H04L27/06 H03D1/02 H03K9/02

    CPC分类号: H04L27/06

    摘要: A digital demodulator of data signals transmitted by linear amplitude modulation of a carrier, sampled under the control of clock pulses CK1, comprises an interpolating unit UIN including a tapped delay line TDL whose outputs carry, at a given instant, respective signal samples received during different clock cycles. These signal samples are fed to a transversal filter FIN also receiving two sets of interpolation coefficients a.sub.k, b.sub.k read out from respective memory sections ME1, ME2. The signal samples from the several delay-line taps are multiplied in filter FIN by the two sets of coefficients a.sub.k and b.sub.k, under the control of a pulse train CK2 and another pulse train CK3 of the same cadence but phase-shifted with reference to the former, and the two sets of resulting products are respectively summed in a digital adder SM and alternately read out to a phase corrector CJ recovering the phase coherence of the demodulated baseband signal.

    摘要翻译: 通过在时钟脉冲CK1的控制下采样的载波的线性幅度调制发送的数据信号的数字解调器包括内插单元UIN,其包括抽头延迟线TDL,其输出在给定时刻承载在不同的时间脉冲 时钟周期。 这些信号样本被馈送到横向滤波器FIN,其也接收从各个存储器部分ME1,ME2读出的两组内插系数ak,bk。 来自多个延迟线抽头的信号采样在脉冲序列CK2和相同节奏的另一个脉冲串CK3的控制下通过两组系数ak和bk在滤波器FIN中相乘,但是相对于 前者和两组产生的产品分别在数字加法器SM中求和,并交替地读出到恢复解调的基带信号的相位相干性的相位校正器CJ。