公开(公告)号：US08359281B2

公开(公告)日：2013-01-22

申请号：US12478073

申请日：2009-06-04

Applicant: Srihari Cadambi ,  Igor Durdanovic ,  Venkata Jakkula ,  Eric Cosatto ,  Murugan Sankaradass ,  Hans Peter Graf ,  Srimat T. Chakradhar

Inventor： Srihari Cadambi ,  Igor Durdanovic ,  Venkata Jakkula ,  Eric Cosatto ,  Murugan Sankaradass ,  Hans Peter Graf ,  Srimat T. Chakradhar

IPC: G06F15/18

CPC classification number: G06N99/005

Abstract: A method system for training an apparatus to recognize a pattern includes providing the apparatus with a host processor executing steps of a machine learning process; providing the apparatus with an accelerator including at least two processors; inputting training pattern data into the host processor; determining coefficient changes in the machine learning process with the host processor using the training pattern data; transferring the training data to the accelerator; determining kernel dot-products with the at least two processors of the accelerator using the training data; and transferring the dot-products back to the host processor.

Abstract translation: 用于训练识别模式的装置的方法系统包括向所述装置提供执行机器学习过程的步骤的主机处理器; 向所述设备提供包括至少两个处理器的加速器; 将训练模式数据输入到主处理器中; 使用所述训练模式数据来确定主处理器在机器学习过程中的系数变化; 将训练数据传送到加速器; 使用所述训练数据确定具有所述加速器的所述至少两个处理器的内核点产品; 并将点产品传送回主机处理器。

公开(公告)号：US20090304268A1

公开(公告)日：2009-12-10

申请号：US12478073

申请日：2009-06-04

Applicant: Srihari Cadambi ,  Igor Durdanovic ,  Venkata Jakkula ,  Eric Cosatto ,  Murugan Sankaradass ,  Hans Peter Graf ,  Srimat T. Chakradhar

Inventor： Srihari Cadambi ,  Igor Durdanovic ,  Venkata Jakkula ,  Eric Cosatto ,  Murugan Sankaradass ,  Hans Peter Graf ,  Srimat T. Chakradhar

IPC: G06K9/62 ,  G06K9/00

CPC classification number: G06N99/005

Abstract: A method system for training an apparatus to recognize a pattern includes providing the apparatus with a host processor executing steps of a machine learning process; providing the apparatus with an accelerator including at least two processors; inputting training pattern data into the host processor; determining coefficient changes in the machine learning process with the host processor using the training pattern data; transferring the training data to the accelerator; determining kernel dot-products with the at least two processors of the accelerator using the training data; and transferring the dot-products back to the host processor.

Abstract translation: 用于训练识别模式的装置的方法系统包括向所述装置提供执行机器学习过程的步骤的主机处理器; 向所述设备提供包括至少两个处理器的加速器; 将训练模式数据输入到主处理器中; 使用所述训练模式数据来确定主处理器在机器学习过程中的系数变化; 将训练数据传送到加速器; 使用所述训练数据确定具有所述加速器的所述至少两个处理器的内核点产品; 并将点产品传送回主机处理器。

公开(公告)号：US07302543B2

公开(公告)日：2007-11-27

申请号：US10869985

申请日：2004-06-16

Applicant: Haris Lekatsas ,  Joerg Henkel ,  Srimat Chakradhar ,  Venkata Jakkula

Inventor： Haris Lekatsas ,  Joerg Henkel ,  Srimat Chakradhar ,  Venkata Jakkula

IPC: G06F12/00

CPC classification number: G06F12/0802 ,  G06F2212/401 ,  H03M7/30

Abstract: An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.

Abstract translation: 公开了可以灵活地处理指令代码和数据的压缩的嵌入式系统架构。

公开(公告)号：US07203935B2

公开(公告)日：2007-04-10

申请号：US10309824

申请日：2002-12-05

Applicant: Srimat Chakradhar ,  Jörg Henkel ,  Venkata Jakkula ,  Haris Lekatsas ,  Murugan Sankaradass

Inventor： Srimat Chakradhar ,  Jörg Henkel ,  Venkata Jakkula ,  Haris Lekatsas ,  Murugan Sankaradass

IPC: G06F9/45 ,  G06F9/30

CPC classification number: G06F9/32 ,  G06F9/30178 ,  G06F9/445

Abstract: A method for code compression of a program, the method comprising separating code from data. Software transformations necessary to make address mappings between compressed and uncompressed space are introduced into the code. Statistics are obtained about frequency of occurrence instructions, wherein said statistics include frequency of occurrence of two consecutive instructions. The program is parsed to identify occurrence of instructions or instruction pairs. The identified instructions are replaced with an address to a compressed bus-word table. An address mapping is generated from uncompressed address to compressed addresses.

Abstract translation: 一种用于程序的代码压缩的方法，所述方法包括从数据中分离代码。 在压缩和未压缩空间之间进行地址映射所需的软件转换被引入到代码中。 获得关于发生指令频率的统计，其中所述统计包括两个连续指令的出现频率。 该程序被解析以识别指令或指令对的发生。 所识别的指令被替换为压缩总线字表的地址。 从未压缩地址到压缩地址生成地址映射。

公开(公告)号：US20060002555A1

公开(公告)日：2006-01-05

申请号：US10869984

申请日：2004-06-16

Applicant: Haris Lekatsas ,  Joerg Henkel ,  Srimat Chakradhar ,  Venkata Jakkula

Inventor： Haris Lekatsas ,  Joerg Henkel ,  Srimat Chakradhar ,  Venkata Jakkula

IPC: H04K1/00

CPC classification number: G06F12/0802 ,  G06F12/121 ,  G06F2212/401 ,  Y10S707/99942

Abstract: An architecture for content-aware compression and/or encryption of various segments of a application is disclosed. The architecture advantageously allows decompression and decryption units to be placed various levels of a memory hierarchy.

公开(公告)号：US07474750B2

公开(公告)日：2009-01-06

申请号：US10869984

申请日：2004-06-16

Applicant: Haris Lekatsas ,  Joerg Henkel ,  Srimat Chakradhar ,  Venkata Jakkula

Inventor： Haris Lekatsas ,  Joerg Henkel ,  Srimat Chakradhar ,  Venkata Jakkula

IPC: H04K1/00

CPC classification number: G06F12/0802 ,  G06F12/121 ,  G06F2212/401 ,  Y10S707/99942

Abstract: An architecture for content-aware compression and/or encryption of various segments of a application is disclosed. The architecture advantageously allows decompression and decryption units to be placed various levels of a memory hierarchy.

Abstract translation: 公开了一种用于应用的各个段的内容感知压缩和/或加密的架构。 该架构有利地允许解压缩和解密单元被放置在存储器层级的各种级别中。

公开(公告)号：US20060101223A1

公开(公告)日：2006-05-11

申请号：US10869985

申请日：2004-06-16

Applicant: Haris Lekatsas ,  Joerg Henkel ,  Srimat Chakradhar ,  Venkata Jakkula

Inventor： Haris Lekatsas ,  Joerg Henkel ,  Srimat Chakradhar ,  Venkata Jakkula

IPC: G06F12/14

CPC classification number: G06F12/0802 ,  G06F2212/401 ,  H03M7/30

Abstract: An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.

Abstract translation: 公开了可以灵活地处理指令代码和数据的压缩的嵌入式系统架构。

公开(公告)号：US20060069857A1

公开(公告)日：2006-03-30

申请号：US11095221

申请日：2005-03-31

Applicant: Haris Lekatsas ,  Joerg Henkel ,  Venkata Jakkula ,  Srimat Chakradhar

Inventor： Haris Lekatsas ,  Joerg Henkel ,  Venkata Jakkula ,  Srimat Chakradhar

IPC: G06F12/00

CPC classification number: H03M7/30 ,  H03M7/3084

Abstract: A new compression and decompression architecture is herein disclosed which advantageously uses a plurality of parallel content addressable memories of different sizes to perform fast matching during compression.

Abstract translation: 本文公开了一种新的压缩和解压缩架构，其有利地使用不同大小的多个并行内容可寻址存储器，以在压缩期间执行快速匹配。

公开(公告)号：US20060005047A1

公开(公告)日：2006-01-05

申请号：US10869983

申请日：2004-06-16

Applicant: Haris Lekatsas ,  Joerg Henkel ,  Srimat Chakradhar ,  Venkata Jakkula

Inventor： Haris Lekatsas ,  Joerg Henkel ,  Srimat Chakradhar ,  Venkata Jakkula

IPC: G06F11/30

CPC classification number: G06F12/1408 ,  G06F12/0875 ,  G06F21/79 ,  G06F21/85 ,  G06F2212/401

Abstract: A system architecture is disclosed that can support fast random access to encrypted memory.

Abstract translation: 公开了可以支持对加密存储器的快速随机访问的系统架构。

公开(公告)号：US06892292B2

公开(公告)日：2005-05-10

申请号：US10135575

申请日：2002-05-01

Applicant: Joerg Henkel ,  Haris Lekatsas ,  Venkata Jakkula

Inventor： Joerg Henkel ,  Haris Lekatsas ,  Venkata Jakkula

IPC: G06F5/00 ,  G06F9/30 ,  G06F9/318

CPC classification number: G06F9/30178

Abstract: Code compression is known as an effective technique to reduce instruction memory size on an embedded system. However, code compression can also be very effective in increasing the processor-to-memory bandwidth and hence provide increased system performance. A code decompression engine having plurality of dictionary tables, coupled with decoding circuitry and appropriate control circuitry, is coupled between the processor core and the instruction cache. The code decompression engine provides one-cycle decompression of compressed instructions that are intermixed with uncompressed instructions, thereby increasing processor-to-memory bandwidth and avoiding processor stalls.

Abstract translation: 已知代码压缩是减少嵌入式系统指令存储器大小的有效技术。 然而，代码压缩在提高处理器到存储器带宽方面也是非常有效的，因此提供了增加的系统性能。 具有与解码电路和适当控制电路耦合的多个字典表的代码解压缩引擎耦合在处理器核心和指令高速缓存之间。 代码解压缩引擎提供与未压缩指令混合的压缩指令的一周期解压缩，从而增加处理器到存储器的带宽并避免处理器停顿。