公开(公告)号：US20070285298A1

公开(公告)日：2007-12-13

申请号：US11760778

申请日：2007-06-10

Applicant: Prakash EASWARAN ,  Prasun BHATTACHARYA ,  Venkatesh T.S

Inventor： Prakash EASWARAN ,  Prasun BHATTACHARYA ,  Venkatesh T.S

IPC: H03M1/12

CPC classification number: H03M1/0604 ,  H03M1/168

Abstract: Methods and systems for designing a high resolution ADC by eliminating the errors in the ADC stages. An error correction architecture and method of the embodiments of the invention eliminate the gain error and settling error of the residue amplifier in a pipelined ADC stage. A reference voltage error correction architecture and method of the embodiments of the invention eliminate the reference voltage error due to the sampling action in the ADC. The gain error correction method calculates the gain error using an error amplifier and eliminates the gain error at a later stage of the ADC. The reference voltage error correction method calculates the reference voltage error using an ideal reference voltage and corrects the error at a later stage of the ADC. The constraints of gain and settling of the residue amplifier is significantly reduced using the embodiments of the invention.

Abstract translation: 通过消除ADC阶段的错误来设计高分辨率ADC的方法和系统。 本发明的实施例的纠错体系结构和方法消除了在流水线ADC级中的残差放大器的增益误差和稳定误差。 本发明的实施例的参考电压误差校正架构和方法消除了由ADC中的采样动作导致的参考电压误差。 增益误差校正方法使用误差放大器计算增益误差，消除ADC后期的增益误差。 参考电压误差校正方法使用理想的参考电压计算参考电压误差，并在ADC后期校正误差。 使用本发明的实施例，残余放大器的增益和稳定的约束显着降低。