公开(公告)号：US20150311913A1

公开(公告)日：2015-10-29

申请号：US14266465

申请日：2014-04-30

Applicant: Broadcom Corporation

Inventor： Hui Pan ,  Karim Abdelhalim

IPC: H03M1/44 ,  H03K17/08

CPC classification number: H03K17/08 ,  H03M1/1245 ,  H03M1/168 ,  H03M1/38 ,  H03M1/468

Abstract: Systems, apparatuses, and methods are provided for analog-to-digital converters (ADCs), such as successive-approximation-register (SAR) ADCs and pipelined ADCs that utilize distributed virtual-ground switching (DVS). DVS circuits and systems receive reference signal inputs that are provided to input signal buffers at the input side of the buffers via reference switches. The input signal buffers and corresponding switches are distributed into scaled replicas that each receive an analog input signal via input signal switches during a first operational phase and are connected to top plates of corresponding distributed capacitors. The bottom plates of the capacitors are sampled to provide analog input signal representations. Based on the value of the signal representations, a state machine controls each of the switches to apply reference signals to the input buffers, during a second operation phase, and to iteratively generate additional signal representations and provide a digital signal that corresponds to the analog input signal.

Abstract translation: 为模数转换器（ADC）提供系统，装置和方法，例如逐次逼近寄存器（SAR）ADC和利用分布式虚拟地交换（DVS）的流水线ADC。 DVS电路和系统接收通过参考开关提供给缓冲器输入端的输入信号缓冲器的参考信号输入。 输入信号缓冲器和相应的开关分配到缩放副本中，每个复本在第一操作阶段通过输入信号开关接收模拟输入信号，并连接到相应的分布式电容器的顶板。 电容器的底板被采样以提供模拟输入信号表示。 基于信号表示的值，状态机控制每个开关以在第二操作阶段期间将参考信号施加到输入缓冲器，并且迭代地产生附加的信号表示并提供对应于模拟输入的数字信号 信号。

公开(公告)号：US09136856B1

公开(公告)日：2015-09-15

申请号：US14191012

申请日：2014-02-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manar Ibrahim El-Chammas

IPC: H03M1/10 ,  H03M1/66 ,  H03M1/12

CPC classification number: H03M1/1057 ,  H03M1/168

Abstract: A circuit includes a track and hold (T/H) block to track an analog input signal during a track phase and to hold the analog input signal during a hold phase. A pipelined converter stage includes an analog to digital converter (ADC) receives the analog input signal from the T/H block and generates a digital output signal corresponding to the analog input signal. A digital to analog converter (DAC) element in the pipelined converter stage receives the digital output signal from the ADC and generates a current output signal representing an analog value for a portion of the analog input signal. A detector monitors the current output signal of the DAC element with respect to a predetermined reference current during the track phase and generates a trim signal if the current output signal is different from the predetermined reference current.

Abstract translation: 电路包括跟踪和保持（T / H）块，用于在跟踪期间跟踪模拟输入信号，并在保持阶段保持模拟输入信号。 流水线转换器级包括模数转换器（ADC）从T / H块接收模拟输入信号，并产生对应于模拟输入信号的数字输出信号。 流水线转换器级中的数模转换器（DAC）元件接收来自ADC的数字输出信号，并产生表示模拟输入信号的一部分的模拟值的电流输出信号。 如果电流输出信号不同于预定参考电流，则检测器在轨道相位期间相对于预定参考电流监测DAC元件的当前输出信号，并产生微调信号。

公开(公告)号：US08660506B2

公开(公告)日：2014-02-25

申请号：US13607365

申请日：2012-09-07

Applicant: Masanori Furuta ,  Hirotomo Ishii

Inventor： Masanori Furuta ,  Hirotomo Ishii

IPC: G06F3/033 ,  H04K3/00

CPC classification number: H03M1/168 ,  H03M1/162 ,  H03M1/361 ,  H03M1/804

Abstract: There is provided with a residual signal generating circuit in which the capacitive DA converter generates a first difference signal with respect to an input signal based on a criterion voltage, the criterion voltage being indicative of an input range of the input signal, the reference voltage generating circuit divides the criterion voltage to obtain at least one partial voltage signal, the residual signal generating section generates 2N−1 first residual signal according to a difference between the first difference signal and 2N−1−1 first reference signal, the 2N−1−1 first reference signal being 2N−1−1 partial voltage signal among said at least one partial voltage signal generated by the reference voltage generating circuit, the comparator compares the 2N−1 first residual signal with a fixed voltage to obtain 2N−1 first comparison signal each indicative of a logical value, and the decoder decodes the 2N−1 first comparison signal to obtain first data of N bits.

Abstract translation: 设置有残留信号发生电路，其中电容DA转换器基于标准电压产生相对于输入信号的第一差分信号，标准电压指示输入信号的输入范围，产生参考电压 电路划分标准电压以获得至少一个部分电压信号，残差信号产生部分根据第一差信号和2N-1-1第一参考信号之间的差产生2N-1个第一残差信号， 1个第一参考信号是由参考电压产生电路产生的所述至少一个部分电压信号中的2N-1-1个部分电压信号，比较器将2N-1个第一残差信号与固定电压进行比较，以获得2N-1个第一比较 信号，每个指示逻辑值，并且解码器解码2N-1个第一比较信号以获得N位的第一数据。

公开(公告)号：US08629797B2

公开(公告)日：2014-01-14

申请号：US13411018

申请日：2012-03-02

Applicant: Kunihiko Gotoh

Inventor： Kunihiko Gotoh

IPC: H03M1/12

CPC classification number: H03M1/06 ,  H03M1/162 ,  H03M1/168

Abstract: A switched capacitor circuit, which is operable in two or more kinds of operation modes including a first and second operation modes, includes an amplifier and two or more internal capacitors with switches for controlling connection/disconnection of the capacitor. In the first operation mode that precedes the second operation mode, the switched capacitor circuit generates the first analog output voltage by using the first internal capacitor connected between an input terminal and output terminal of the amplifier by using its switches, the other internal capacitances connected between an input terminal of the amplifier and each analog input voltage supply by using its switches. In the second operation mode, the switched capacitor circuit generates the second analog output voltage with larger feedback factor of the amplifier than it in the first operation mode, by removing some of the internal capacitors, except the first internal capacitor, from the first operation mode.

Abstract translation: 可以在包括第一和第二操作模式的两种或多种操作模式中操作的开关电容器电路包括放大器和具有用于控制电容器的连接/断开的开关的两个或更多个内部电容器。 在第二操作模式之前的第一操作模式中，开关电容器电路通过使用通过使用其开关连接在放大器的输入端子和输出端子之间的第一内部电容器来产生第一模拟输出电压，其他内部电容连接在 放大器的输入端和使用其开关的每个模拟输入电压电源。 在第二操作模式中，通过从第一操作模式除去第一内部电容器之外的一些内部电容器，除了第一操作模式之外，开关电容器电路产生具有比第一操作模式更大的反馈系数的第二模拟输出电压 。

公开(公告)号：US08497794B2

公开(公告)日：2013-07-30

申请号：US13435173

申请日：2012-03-30

Applicant: Shinichirou Etou ,  Yasuhide Shimizu ,  Kouhei Kudou ,  Yukitoshi Yamashita

Inventor： Shinichirou Etou ,  Yasuhide Shimizu ,  Kouhei Kudou ,  Yukitoshi Yamashita

IPC: H03M1/38

CPC classification number: H03M1/0604 ,  H03G1/0029 ,  H03M1/0682 ,  H03M1/168

Abstract: An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.

Abstract translation: AD转换器包括：AD转换级，被配置为产生数字数据，该数字数据具有与被输入的两个模拟信号之间的关系的值，并且与第一放大器放大两个模拟残差信号;以及第二放大器，其具有待控制的增益以输出信号; 以及增益控制部，其被配置为基于所述第一放大器和所述第二放大器的输出信号的监视结果来控制所述第一放大器和所述第二放大器的增益。 第一放大器和第二放大器由开环放大器形成，并且增益控制部分在至少一个AD转换级中取出第一放大器和第二放大器的输出信号的幅度信息，并执行增益控制 从阶段输出的模拟信号的幅度在设定的设定幅度上收敛。

公开(公告)号：US20130183920A1

公开(公告)日：2013-07-18

申请号：US13607365

申请日：2012-09-07

Applicant: Masanori FURUTA ,  Hirotomo Ishii

Inventor： Masanori FURUTA ,  Hirotomo Ishii

IPC: H03M1/38 ,  H04B1/18 ,  H03M1/66

CPC classification number: H03M1/168 ,  H03M1/162 ,  H03M1/361 ,  H03M1/804

Abstract: There is provided with a residual signal generating circuit in which the capacitive DA converter generates a first difference signal with respect to an input signal based on a criterion voltage, the criterion voltage being indicative of an input range of the input signal, the reference voltage generating circuit divides the criterion voltage to obtain at least one partial voltage signal, the residual signal generating section generates 2N−1 first residual signal according to a difference between the first difference signal and 2N−1−1 first reference signal, the 2N−1−1 first reference signal being 2N−1−1 partial voltage signal among said at least one partial voltage signal generated by the reference voltage generating circuit, the comparator compares the 2N−1 first residual signal with a fixed voltage to obtain 2N−1 first comparison signal each indicative of a logical value, and the decoder decodes the 2N−1 first comparison signal to obtain first data of N bits.

Abstract translation: 设置有残留信号发生电路，其中电容DA转换器基于标准电压产生相对于输入信号的第一差分信号，标准电压指示输入信号的输入范围，产生参考电压 电路划分标准电压以获得至少一个部分电压信号，残差信号产生部分根据第一差信号和2N-1-1第一参考信号之间的差产生2N-1个第一残差信号， 1个第一参考信号是由参考电压产生电路产生的所述至少一个部分电压信号中的2N-1-1个部分电压信号，比较器将2N-1个第一残差信号与固定电压进行比较，以获得2N-1个第一比较 信号，每个指示逻辑值，并且解码器解码2N-1个第一比较信号以获得N位的第一数据。

公开(公告)号：US08471753B1

公开(公告)日：2013-06-25

申请号：US13034813

申请日：2011-02-25

Applicant: Yen-Chuan Huang ,  Tai-Cheng Lee

Inventor： Yen-Chuan Huang ,  Tai-Cheng Lee

IPC: H03M1/38

CPC classification number: H03M1/1225 ,  H03M1/168

Abstract: A pipelined analog-to-digital converter with less power consumption is provided. In one embodiment, the pipelined analog-to-digital converter comprises a first stage, a second stage, and a third stage. The first stage receives a first stage input signal to derive a first stage output signal and a first residue. The second stage receives a second stage input signal to derive a second stage output signal and a second residue, wherein the second stage input signal corresponds to the first residue. The third stage receives a third stage input signal to derive a third stage output signal and a third residue, wherein the third stage input signal corresponds to the second residue. The first, second and third stages share an operational amplifier by utilizing at least three phases to control the operational amplifier.

Abstract translation: 提供了具有较少功耗的流水线模数转换器。 在一个实施例中，流水线模数转换器包括第一级，第二级和第三级。 第一级接收第一级输入信号以导出第一级输出信号和第一级残差。 第二级接收第二级输入信号以导出第二级输出信号和第二残差，其中第二级输入信号对应于第一级残差。 第三级接收第三级输入信号以导出第三级输出信号和第三残差，其中第三级输入信号对应于第二级残差。 第一，第二和第三级通过利用至少三个相位来控制运算放大器来共享运算放大器。

公开(公告)号：US20130135127A1

公开(公告)日：2013-05-30

申请号：US13741078

申请日：2013-01-14

Applicant: Analog Devices, Inc.

Inventor： Eric John SIRAGUSA

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/0695 ,  H03M1/1033 ,  H03M1/168

Abstract: A stage of a pipelined analog-to-digital converter can include first and second pluralities of digital-to-analog converters (DACs), the first plurality sufficient in number to produce a residue from the stage, the second plurality having their outputs added into an analog output of the stage. A mapping circuit can exchange inputs between selected ones of the first and second pluralities of DACs, and a calibration circuit can provide first and second calibration signals to the selected one of the first plurality and another of the second plurality of DACs. The calibration signals can correlate to each other, but be uncorrelated to an analog input and digital output of the stage, and have unequal and partially offsetting effects on the stage's residue. A correction circuit can correct the digital output of the stage for circuit path errors based on a correlation between the calibration signals and an output of a succeeding stage.

Abstract translation: 流水线模数转换器的级可以包括第一和第二多个数模转换器（DAC），第一个数量足以产生来自该级的残留，第二个多个具有加到其中的输出 舞台的模拟输出。 映射电路可以在第一和第二多个DAC中的所选择的DAC之间交换输入，并且校准电路可以向第二多个DAC中的第一和第二多个DAC中的所选择的一个提供第一和第二校准信号。 校准信号可以彼此相关，但与舞台的模拟输入和数字输出不相关，并且对舞台的残差具有不相等和部分抵消的影响。 校正电路可以基于校准信号与后级的输出之间的相关性来校正电路路径误差的级的数字输出。

公开(公告)号：US08339303B2

公开(公告)日：2012-12-25

申请号：US13094280

申请日：2011-04-26

Applicant: Ahmed Mohamed Abdelatty Ali ,  Huseyin Dinc ,  Paritosh Bhoraskar

Inventor： Ahmed Mohamed Abdelatty Ali ,  Huseyin Dinc ,  Paritosh Bhoraskar

IPC: H03M1/34

CPC classification number: H03M1/002 ,  H03M1/1057 ,  H03M1/168

Abstract: An integrated circuit allows for the isolation of the input of an analog-to-digital converter (ADC) from a summing-node (SNS) algorithm. The integrated circuit contains a gating device that is controlled by bits of a flash analog-to-digital converter (ADC) to gate input samples to sub-ranges that are used by the SNS algorithm. A single sub-range is chosen to be used by the SNS algorithm.

Abstract translation: 集成电路允许从求和节点（SNS）算法隔离模数转换器（ADC）的输入。 该集成电路包含由闪存模数转换器（ADC）的位控制到门输入采样到由SNS算法使用的子范围的门控器件。 选择单个子范围以供SNS算法使用。

公开(公告)号：US20120299758A1

公开(公告)日：2012-11-29

申请号：US13479592

申请日：2012-05-24

Applicant: Won Seok HWANG ,  Seung Hoon LEE ,  Jung Eun SONG ,  Dong Hyun HWANG

Inventor： Won Seok HWANG ,  Seung Hoon LEE ,  Jung Eun SONG ,  Dong Hyun HWANG

IPC: H03M1/00

CPC classification number: H03M1/145 ,  H03F1/0261 ,  H03F3/45 ,  H03F3/45183 ,  H03M1/1225 ,  H03M1/168

Abstract: An analog to digital converting device includes a first digital conversion (ADC) circuit configured to convert an inputted analog signal into a first digital signal, a first multiplying digital to analog converting (MDAC) circuit configured to amplify a difference between a first converted signal and the inputted analog signal, a second ADC circuit configured to convert an output of the first MDAC circuit into a second digital signal, a second MDAC circuit configured to amplify difference between a second converted signal converted from the second digital signal and the output of the first MDAC circuit, a third ADC circuit configured to convert an output of the second MDAC circuit into a third digital signal, and a common amplifying circuit shared by the first and the second MDAC circuits, wherein the common amplifying circuit consumes current based on which MDAC circuit the common amplifying circuit operates with.

Abstract translation: 模数转换装置包括：第一数字转换（ADC）电路，被配置为将输入的模拟信号转换为第一数字信号;第一乘法数/模转换（MDAC）电路，被配置为放大第一转换信号和 输入的模拟信号，被配置为将第一MDAC电路的输出转换为第二数字信号的第二ADC电路，被配置为放大从第二数字信号转换的第二转换信号与第一数字信号的输出之间的差的第二MDAC电路 MDAC电路，被配置为将第二MDAC电路的输出转换为第三数字信号的第三ADC电路和由第一和第二MDAC电路共用的公共放大电路，其中，所述公共放大电路基于哪个MDAC电路消耗电流 公共放大电路与。