公开(公告)号：US07821436B2

公开(公告)日：2010-10-26

申请号：US11760743

申请日：2007-06-09

申请人： Venkatesh Teeka Srinvasa Setty ,  Chandrashekar Lakshminarayanan ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  Chakravarthy Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

发明人： Venkatesh Teeka Srinvasa Setty ,  Chandrashekar Lakshminarayanan ,  Prasun Kali Bhattacharya ,  Prasenjit Bhowmik ,  Chakravarthy Srinivasan ,  Mukesh Khatri ,  Sanjeeb Kumar Ghosh ,  Sumanth Chakkirala ,  Sundararajan Krishnan ,  Prakash Easwaran

IPC分类号： H03M3/00

CPC分类号： H03M1/0641 ,  H03M1/12

摘要： A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

摘要翻译： 一种降低模数转换器（ADC）功耗的系统和方法。 该方法包括以下步骤：从多个时钟相位的前一相位接收残留输出，其中多个时钟相位包括采样保持相位和用于分别对模拟输入信号进行采样和放大的放大相位，消除 当放大残留物输出时，负载对残留放大器的影响，以在放大阶段产生放大的残留输出，并且在取样和保持阶段中对放大的残留输出进行采样时，消除小的反馈因子的影响。 通过在采样保持阶段和放大阶段共享残留放大器上的负载而不是完全存在于任何一个时钟相位来实现功率优点。 本发明还提供了一种减少ADC中使用的比较器数量的方法。