公开(公告)号：US20190042249A1

公开(公告)日：2019-02-07

申请号：US15943654

申请日：2018-04-02

申请人： VIKRAM SURESH ,  SANU MATHEW ,  SUDHIR SATPATHY ,  VINODH GOPAL

发明人： VIKRAM SURESH ,  SANU MATHEW ,  SUDHIR SATPATHY ,  VINODH GOPAL

IPC分类号： G06F9/30 ,  G06F9/38 ,  H04L9/06

摘要： Methods and apparatuses relating to high-performance authenticated encryption are described. A hardware accelerator may include a vector register to store an input vector of a round of an encryption operation; a circuit including a first data path including a first modular adder coupled to a first input from the vector register and a second input from the vector register, and a second modular adder coupled to the first modular adder and a second data path from the vector register, and the second data path including a first logical XOR circuit coupled to the second input and a third data path from the vector register, a first rotate circuit coupled to the first logical XOR circuit, a second logical XOR circuit coupled to the first rotate circuit and the third data path, and a second rotate circuit coupled to the second logical XOR circuit; and a control circuit to cause the first modular adder and the second modular adder of the first data path and the first logical XOR circuit, the second logical XOR circuit, the first rotate circuit, and the second rotate circuit of the second data path to perform a portion of the round according to one or more control values, and store a first result from the first data path for the portion and a second result from the second data path for the portion into the vector register.

公开(公告)号：US09013949B2

公开(公告)日：2015-04-21

申请号：US13330172

申请日：2011-12-19

申请人： Russell Schreiber ,  Vikram Suresh

发明人： Russell Schreiber ,  Vikram Suresh

IPC分类号： G11C8/08 ,  G11C11/418

CPC分类号： G11C11/418 ,  G11C8/08

摘要： The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request operative to write data to at least one memory cell of a plurality of memory cells, increasing a word line voltage above a nominal level after a predetermined delay following the receipt of the write request. A disclosed system includes a word line driver operative to increase a word line voltage above a nominal level during a write access after a predetermined delay in response to a write request.

摘要翻译： 本公开涉及一种用于控制存储器访问的方法和系统。 特别地，一种用于控制存储器存取的方法包括：响应于接收到写入请求，该写入请求可操作以将数据写入多个存储器单元中的至少一个存储单元，在经过预定的延迟之后将字线电压增加到标称电平以上 收到写请求。 所公开的系统包括字符串驱动器，其在响应于写入请求的预定延迟之后在写入访问期间将字线电压增加到额定电平以上。

公开(公告)号：US20130155793A1

公开(公告)日：2013-06-20

申请号：US13330172

申请日：2011-12-19

申请人： Russell Schreiber ,  Vikram Suresh

发明人： Russell Schreiber ,  Vikram Suresh

IPC分类号： G11C7/00

CPC分类号： G11C11/418 ,  G11C8/08

摘要： The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request operative to write data to at least one memory cell of a plurality of memory cells, increasing a word line voltage above a nominal level after a predetermined delay following the receipt of the write request. A disclosed system includes a word line driver operative to increase a word line voltage above a nominal level during a write access after a predetermined delay in response to a write request.

摘要翻译： 本公开涉及一种用于控制存储器访问的方法和系统。 特别地，一种用于控制存储器存取的方法包括：响应于接收到写入请求，该写入请求可操作以将数据写入多个存储器单元中的至少一个存储单元，在经过预定的延迟之后将字线电压增加到标称电平以上 收到写请求。 所公开的系统包括字符串驱动器，其在响应于写入请求的预定延迟之后在写入访问期间将字线电压增加到额定电平以上。

公开(公告)号：US20150086007A1

公开(公告)日：2015-03-26

申请号：US14035508

申请日：2013-09-24

申请人： Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

发明人： Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

IPC分类号： H04L9/30

CPC分类号： H04L9/0631 ,  H04L2209/24

摘要： Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.

摘要翻译： 公开了一种用于紧凑型低功率高级加密标准电路的发明的实施例。 在一个实施例中，装置包括具有替换盒和累加器的加密单元。 替代方案是对每个时钟周期的一个字节执行替换操作。 累加器将累积四个字节，并在四个时钟周期内执行混合列操作。 加密单元使用最小区域的最优伽罗瓦域多项式运算来实现。