公开(公告)号：US20250098179A1

公开(公告)日：2025-03-20

申请号：US18467984

申请日：2023-09-15

Applicant: Abhishek A. Sharma ,  Van H. Le ,  Fatih Hamzaoglu ,  Juan G. Alzate-Vinasco ,  Nikhil Jasvant Mehta ,  Vinaykumar Hadagali ,  Yu-Wen Huang ,  Honore Djieutedjeu ,  Tahir Ghani ,  Timothy Jen ,  Shailesh Kumar Madisetti ,  Jisoo Kim ,  Wilfred Gomes ,  Kamal Baloch ,  Vamsi Evani ,  Christopher Wiegand ,  James Pellegren ,  Sagar Suthram ,  Christopher M. Pelto ,  Gwang Soo Kim ,  Babita Dhayal ,  Prashant Majhi ,  Anand Iyer ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Pooya Tadayon ,  Nitin A. Deshpande

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Fatih Hamzaoglu ,  Juan G. Alzate-Vinasco ,  Nikhil Jasvant Mehta ,  Vinaykumar Hadagali ,  Yu-Wen Huang ,  Honore Djieutedjeu ,  Tahir Ghani ,  Timothy Jen ,  Shailesh Kumar Madisetti ,  Jisoo Kim ,  Wilfred Gomes ,  Kamal Baloch ,  Vamsi Evani ,  Christopher Wiegand ,  James Pellegren ,  Sagar Suthram ,  Christopher M. Pelto ,  Gwang Soo Kim ,  Babita Dhayal ,  Prashant Majhi ,  Anand Iyer ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Pooya Tadayon ,  Nitin A. Deshpande

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.