公开(公告)号：US20150237713A1

公开(公告)日：2015-08-20

申请号：US14184575

申请日：2014-02-19

申请人： Adel A. Elsherbini ,  Ravindranath Mahajan ,  John S. Guzek ,  Nitin A. Deshpande

发明人： Adel A. Elsherbini ,  Ravindranath Mahajan ,  John S. Guzek ,  Nitin A. Deshpande

IPC分类号： H05K1/02 ,  H01L23/13 ,  H01L25/00 ,  H05K3/36 ,  H01L25/065 ,  H05K1/14 ,  H05K1/11 ,  H01L23/552 ,  H01L23/538

CPC分类号： H05K1/147 ,  H01L23/13 ,  H01L23/49833 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/15192 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K3/361 ,  H05K2201/09245 ,  H05K2201/09681 ,  Y10T29/49126

摘要： Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及电磁干扰（EMI）屏蔽技术和配置。 在一个实施例中，一种装置包括第一衬底，具有与第一衬底耦合的互连结构的管芯以在管芯和第一衬底之间路由输入/输出（I / O）信号和与第一衬底耦合的第二衬底， 芯片设置在第一基板和第二基板之间，并且第一基板和第二基板中的至少一个包括被配置为为管芯提供电磁干扰（EMI）屏蔽的迹线。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09607964B2

公开(公告)日：2017-03-28

申请号：US14229788

申请日：2014-03-28

申请人： Omkar G. Karhade ,  Nitin A. Deshpande, Jr. ,  Aditya Sundoctor Vaidya ,  Nachiket R. Raravikar ,  Eric J. Li

发明人： Omkar G. Karhade ,  Nitin A. Deshpande, Jr. ,  Aditya Sundoctor Vaidya ,  Nachiket R. Raravikar ,  Eric J. Li

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L21/565 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/92 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L21/56 ,  H01L2224/81 ,  H01L2224/45099 ,  H01L2924/00012

摘要： Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.

公开(公告)号：US20150001717A1

公开(公告)日：2015-01-01

申请号：US13930082

申请日：2013-06-28

申请人： Omkar G. Karhade ,  Nitin A. Deshpande ,  Rajendra C. Dias ,  Edvin Cetegen ,  Lars D. Skoglund

发明人： Omkar G. Karhade ,  Nitin A. Deshpande ,  Rajendra C. Dias ,  Edvin Cetegen ,  Lars D. Skoglund

IPC分类号： H01L23/31 ,  H01L23/485

CPC分类号： H01L23/485 ,  H01L21/563 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17505 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665

摘要： Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

摘要翻译： 对半导体封装中的管芯间间距减小的底层填充材料流动控制以及所得到的半导体封装进行了描述。 在一个示例中，半导体器件包括第一和第二半导体管芯，每个半导体管芯具有其上具有集成电路的表面，其上通过多个导电触点与公共半导体封装衬底的最上层金属化层的接触焊盘耦合，第一和第二半导体 模具间隔开。 阻挡结构设置在第一半导体管芯和公共半导体封装衬底之间并且至少部分地位于第一半导体管芯的下方。 底部填充材料层与第二半导体管芯和阻挡结构接触，但不与第一半导体管芯接触。

公开(公告)号：US20220199536A1

公开(公告)日：2022-06-23

申请号：US17126636

申请日：2020-12-18

申请人： Omkar G. Karhade ,  Edvin Cetegen ,  Anurag Tripathi ,  Nitin A. Deshpande

发明人： Omkar G. Karhade ,  Edvin Cetegen ,  Anurag Tripathi ,  Nitin A. Deshpande

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

摘要： Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20160268231A1

公开(公告)日：2016-09-15

申请号：US14767471

申请日：2014-09-15

申请人： Omkar G. Karhade ,  Nitin A. Deshpande ,  Edvin Cetegen ,  Eric J. Li ,  Debendra Mallik ,  Bassam M. Ziadeh

发明人： Omkar G. Karhade ,  Nitin A. Deshpande ,  Edvin Cetegen ,  Eric J. Li ,  Debendra Mallik ,  Bassam M. Ziadeh

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3142 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/1815 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/0665

摘要： Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.

摘要翻译： 制造微电子器件的方法包括形成具有多个微电子器件附着接合焊盘的微电子衬底和在其有效表面上和/或其有效表面上形成的至少一个互连接合焊盘，将微电子器件连接到多个微电子器件附接接合焊盘 形成具有模具主体和至少一个从所述模具主体延伸的突起的模具追踪器，其中所述至少一个突出部包括至少一个侧壁和接触表面，所述至少一个突出部将所述模具追踪投影接触表面接触到相应的微电子衬底互连接合 在微电子基板和模具追逐之间设置模具材料，并且通过从模具材料的顶表面延伸到相应的微电子衬底互连接合垫，去除模具追逐以形成至少一个互连。

公开(公告)号：US20150318255A1

公开(公告)日：2015-11-05

申请号：US14266089

申请日：2014-04-30

申请人： OMKAR G. KARHADE ,  NITIN A. DESHPANDE ,  DANISH FARUQUI

发明人： OMKAR G. KARHADE ,  NITIN A. DESHPANDE ,  DANISH FARUQUI

IPC分类号： H01L23/00 ,  H01L21/306 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L21/30604 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/83931 ,  H01L2224/83947 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2924/10156 ,  H01L2924/10158 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81 ,  H01L2224/83 ,  H01L21/306

摘要： Ultrathin microelectronic die packages and methods of fabricating the same comprising attaching a microelectronic die to a substrate with a plurality of interconnects, and depositing an underfill material between the microelectronic die and the microelectronic substrate, and around the interconnects. An etchant may be introduced to a back surface of the microelectronic die to remove a portion thereof which reduces the thickness of the microelectronic die to form an ultrathin microelectronic die. In another embodiment, the etching of the microelectronic die forms an ultrathin microelectronic die having a curved surface between the ultrathin microelectronic die back surface and a sidewall thereof.

摘要翻译： 超薄微电子管芯封装及其制造方法包括将微电子管芯附接到具有多个互连的衬底上，以及在微电子管芯和微电子衬底之间以及在互连件周围沉积底部填充材料。 可以将蚀刻剂引入到微电子管芯的后表面以去除其部分，这减少了微电子管芯的厚度以形成超薄微电子管芯。 在另一个实施例中，微电子管芯的蚀刻形成了超薄微电子管芯，其在超薄微电子管芯背表面和其侧壁之间具有弯曲表面。

公开(公告)号：US20150171015A1

公开(公告)日：2015-06-18

申请号：US14132774

申请日：2013-12-18

申请人： Ravindranath V. Mahajan ,  Christopher J. Nelson ,  Omkar G. Karhade ,  Feras Eid ,  Nitin A. Deshpande ,  Shawna M. Liff

发明人： Ravindranath V. Mahajan ,  Christopher J. Nelson ,  Omkar G. Karhade ,  Feras Eid ,  Nitin A. Deshpande ,  Shawna M. Liff

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L25/16

CPC分类号： H01L23/5381 ,  H01L21/563 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/24145 ,  H01L2224/24245 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/0665

摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及具有分别具有第一和第二输入/输出（I / O）互连结构的第一和第二裸片的集成电路（IC）封装。 IC封装可以包括具有分别耦合到第一和第二I / O互连结构的一部分的第一和第二电路由特征的桥。 在实施例中，第一和第二电路由特征可以设置在桥的一侧; 并且第三电路布线特征可以设置在相对侧上。 第一和第二电路由特征可以被配置为在第一管芯和第二管芯之间路由电信号，并且第三电路由特征可以被配置为在一侧和相对侧之间路由电信号。 第一管芯，第二管芯和桥可以嵌入电绝缘材料中。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140091470A1

公开(公告)日：2014-04-03

申请号：US13631612

申请日：2012-09-28

申请人： Sandeep B. Sane ,  Shandar Ganapathysubramanian ,  Jorge Sanchez ,  Leonel R. Arana ,  Eric J. Li ,  Nitin A. Deshpande ,  Jiraporn Seangatith ,  Poh Chieh Benny Poon

发明人： Sandeep B. Sane ,  Shandar Ganapathysubramanian ,  Jorge Sanchez ,  Leonel R. Arana ,  Eric J. Li ,  Nitin A. Deshpande ,  Jiraporn Seangatith ,  Poh Chieh Benny Poon

IPC分类号： H01L23/00

CPC分类号： H01L24/32 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/3213 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/161 ,  H01L2924/16251 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014

摘要： Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.

摘要翻译： 控制模具翘曲，用于组装薄模具。 在一个示例中，形成具有背面上的基板和在前侧层中的部件的装置。 背衬层形成在衬底上，该层在加热器件时抵抗器件翘曲。 该装置通过加热连接到基板。

公开(公告)号：US07166540B2

公开(公告)日：2007-01-23

申请号：US11072112

申请日：2005-03-03

申请人： Nitin A. Deshpande ,  Sandeep B. Sane

发明人： Nitin A. Deshpande ,  Sandeep B. Sane

IPC分类号： H01L21/31

CPC分类号： H01L21/4882 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method and apparatus for mounting semiconductor die and integral heat spreader are disclosed. In one embodiment, thermal expansion of the integral heat spreader is restricted by physical constraints during the process of heating interface material that bonds the integral heat spreader and semiconductor die together. In an alternative embodiment, thermal expansion of the integral hat spreader is restricted by applying an external compressive force to the integral heat spreader while heating interface material that bonds the integral heat spreader and semiconductor die together.

摘要翻译： 公开了一种用于安装半导体管芯和整体散热器的方法和装置。 在一个实施例中，整体散热器的热膨胀在加热将整体式散热器和半导体管芯结合在一起的界面材料的加工过程中受到物理限制。 在替代实施例中，通过在整体散热器和半导体管芯结合在一起的界面材料的加热的同时，对整体散热器施加外部压缩力来限制整体散热器的热膨胀。

公开(公告)号：US09741692B2

公开(公告)日：2017-08-22

申请号：US14767471

申请日：2014-09-15

申请人： Omkar G. Karhade ,  Nitin A. Deshpande ,  Edvin Cetegen ,  Eric J. Li ,  Debendra Mallik ,  Bassam M. Ziadeh

发明人： Omkar G. Karhade ,  Nitin A. Deshpande ,  Edvin Cetegen ,  Eric J. Li ,  Debendra Mallik ,  Bassam M. Ziadeh

IPC分类号： H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L25/10 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3142 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/1815 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/0665

摘要： Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.