公开(公告)号：US5673389A

公开(公告)日：1997-09-30

申请号：US522476

申请日：1995-08-31

申请人： Charles Francis Weber ,  Viral Ashokkumar Amin

发明人： Charles Francis Weber ,  Viral Ashokkumar Amin

IPC分类号： G06F11/00 ,  G06F11/30

CPC分类号： G06F11/0763 ,  G06F11/0757

摘要： Systems which progress through a series of states or program steps, such as software controlled computers, are monitored by means of a watchdog timer which samples at least two check bits generated by a system being monitored with the check bits being generated such that only one can change its logic state between valid samples of the check bits. The monitored system is reset if a fault within the system results in an error in the normal sequence through the series of states or program steps such that more than one of the check bits changes from sample to sample. In addition, if the sequence becomes static such that no bits change within the check bits from sample to sample, a time-out will occur which also resets the monitored system. Preferably, the check bits are generated in accordance with Gray code.

摘要翻译： 通过看门狗定时器监视通过一系列状态或程序步骤进行的系统，例如软件控制的计算机，其对由正被生成的校验位进行监视的系统产生的至少两个校验位进行采样，使得只有一个可以 在校验位的有效样本之间更改其逻辑状态。 如果系统中的故障导致通过一系列状态或程序步骤的正常序列中的错误，使得多个检查位从样本变为样本，则监视的系统被重置。 此外，如果序列变得静态，使得在从采样到采样的校验位内没有位改变，则会发生超时，这也会使被监视的系统复位。 优选地，校验位根据格雷码产生。