公开(公告)号：US08073058B2

公开(公告)日：2011-12-06

申请号：US12559212

申请日：2009-09-14

申请人： Tetsujiro Kondo ,  Wataru Niitsuma ,  Naoki Kobayashi

发明人： Tetsujiro Kondo ,  Wataru Niitsuma ,  Naoki Kobayashi

IPC分类号： H04N7/12 ,  G06K9/36

CPC分类号： H04N5/145 ,  G06T7/231 ,  G06T2200/28 ,  G06T2207/10016 ,  G11C7/1006 ,  G11C11/565 ,  H04N19/43 ,  H04N19/436 ,  H04N19/51 ,  H04N19/61

摘要： This invention relates to a memory device and the like that are preferably applied to a case where motion vector is detected using a block matching. Pixel data of a first frame (a reference frame) is stored in a unit A of memory cell array portion 20a in straight binary format. Pixel data of a second frame (a search frame) is stored in a unit B of memory cell array portion 20b in two's complement format. The units A and B have a plurality of memory cells, respectively. Word lines WL related to the pixel data of the first and second frames are simultaneously activated so that charges accumulated in capacitors of each of the memory cells can be combined along one bit line BL. A/D converter 53 outputs a digital signal (absolute difference value) having a value that corresponds to a total amount of charges. When reading the pixel data, a subtraction and a conversion into the absolute difference value are simultaneously performed.

摘要翻译： 本发明涉及优选地应用于使用块匹配检测运动矢量的情况的存储器件等。 第一帧（参考帧）的像素数据以直二进制格式存储在存储单元阵列部分20a的单元A中。 第二帧（搜索帧）的像素数据以二进制格式存储在存储单元阵列部分20b的单元B中。 单元A和B分别具有多个存储单元。 与第一和第二帧的像素数据相关的字线WL被同时激活，使得可以沿着一个位线BL组合每个存储单元的电容器中积累的电荷。 A / D转换器53输出具有与总电荷量对应的值的数字信号（绝对差值）。 当读取像素数据时，同时执行减法和转换成绝对差值。

公开(公告)号：US07869085B2

公开(公告)日：2011-01-11

申请号：US10921267

申请日：2004-08-19

申请人： Kohtaro Nemoto ,  Tetsujiro Kondo ,  Nobuyuki Asakura ,  Satoshi Inoue ,  Wataru Niitsuma ,  Tatsuya Ishii ,  Takahide Ayata ,  Masanori Yamanaka ,  Yasushi Tatehira

发明人： Kohtaro Nemoto ,  Tetsujiro Kondo ,  Nobuyuki Asakura ,  Satoshi Inoue ,  Wataru Niitsuma ,  Tatsuya Ishii ,  Takahide Ayata ,  Masanori Yamanaka ,  Yasushi Tatehira

IPC分类号： G06F15/00 ,  G06K15/00 ,  H04N1/405 ,  G03F3/08

CPC分类号： G09G5/005 ,  G09G3/20 ,  G09G5/006 ,  G09G2340/0407

摘要： A luminance signal Ya and a color-difference signal Ua/Va constituting an input image signal is transferred to a frame memory (first memory) in the unit of line synchronously with its horizontal synchronous signal and written therein. A memory TG211 reads out a read-out request RRQ. The cycle of this request RRQ is a time computed based on a single vertical effective period of an output image signal Sc and the number of lines objective for rate conversion of an input image signal Sa. The luminance signal Ya and color-difference signal Ua/Va are transferred in the unit of line from the frame memory to rate conversion units (second memory) through buffers. There occurs no deflection in this transfer cycle and in each transfer cycle, the stable data transmission band can be secured.

摘要翻译： 构成输入图像信号的亮度信号Ya和色差信号Ua / Va与其水平同步信号同步地被传送到帧存储器（第一存储器）并写入其中。 存储器TG211读出读出请求RRQ。 该请求RRQ的周期是基于输出图像信号Sc的单个垂直有效周期和输入图像信号Sa的速率转换的行数目的计算的时间。 亮度信号Ya和色差信号Ua / Va以行为单位从帧存储器传送到速率转换单元（第二存储器）通过缓冲器。 在该传送周期中，在每个传送周期中不发生偏转，可以确保稳定的数据传输带。

公开(公告)号：US07038729B2

公开(公告)日：2006-05-02

申请号：US10204591

申请日：2001-12-26

申请人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Takuo Morimura ,  Nobuyuki Asakura ,  Wataru Niitsuma ,  Kei Hiraizumi ,  Takahide Ayata

发明人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Takuo Morimura ,  Nobuyuki Asakura ,  Wataru Niitsuma ,  Kei Hiraizumi ,  Takahide Ayata

IPC分类号： H04N7/01

CPC分类号： H04N7/0137 ,  G06T3/40 ,  G09G2340/0407 ,  H04N7/0125 ,  H04N7/0145

摘要： The present invention relates to an information signal processor and the like preferable for use in the case of converting a format of an image signal or converting an image size. An input image signal Vin (525i signal) is converted into an output image signal Vout (such as 1080i signal, XGA signal, or 525i signal for obtaining an image to be displayed in a different magnification). A class code CL is obtained from tap data selectively extracted from the Vin and corresponding to each pixel (pixel at a target position) within a unit pixel block, which constitutes Vout. A coefficient production circuit produces coefficient data for each class, which is used at the time of calculating the pixel data at the target position, based on the coefficient seed data for each class and position information h, v about the target position generated in a position information generation circuit. A calculation circuit provides pixel data y1 to yp of the target position according to the estimated equation using the tap data xi corresponding to the target position and the coefficient data Wi corresponding to the class code CL.

摘要翻译： 本发明涉及一种信息信号处理器等，其优选用于转换图像信号的格式或转换图像大小的情况。 输入图像信号Vin（525i信号）被转换为输出图像信号Vout（诸如1080i信号，XGA信号或525i信号，用于获得以不同放大倍率显示的图像）。 根据构成Vout的单位像素块内的每个像素（目标位置的像素），从有选择地从Vin中提取的抽头数据获得类码CL。 系数生成电路基于每个类的系数种子数据和关于在位置上生成的目标位置的位置信息h，v，在计算目标位置处的像素数据时使用的每个类别生成系数数据 信息生成电路。 计算电路使用与目标位置对应的抽头数据xi和与类代码CL对应的系数数据Wi，根据推定的方程，提供目标位置的像素数据y 1至yp。

公开(公告)号：US06483545B1

公开(公告)日：2002-11-19

申请号：US09358272

申请日：1999-07-21

申请人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Nobuyuki Asakura ,  Masashi Uchida ,  Takuo Morimura ,  Kazutaka Ando ,  Hideo Nakaya ,  Tsutomu Watanabe ,  Satoshi Inoue ,  Wataru Niitsuma

发明人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Nobuyuki Asakura ,  Masashi Uchida ,  Takuo Morimura ,  Kazutaka Ando ,  Hideo Nakaya ,  Tsutomu Watanabe ,  Satoshi Inoue ,  Wataru Niitsuma

IPC分类号： H04N701

CPC分类号： H04N7/012 ,  H04N7/0125 ,  H04N7/0137 ,  H04N7/0145

摘要： A 525i (interlace) signal can be converted into a 1050i signal or a 525p (progressive) signal. A calculating circuit generates pixels of an output picture signal with a linear estimation expression of predictive taps received from a tap selecting circuit and a coefficient received from a coefficient memory. The coefficient memory stores coefficients pre-obtained for individual classes. A class is determined by combining a spatial class corresponding to spatial class taps received from a tap selecting circuit and motion class taps received from a tap selecting circuit. A line sequential converting circuit converts a scanning line structure of an output signal of the calculating circuit 34 and obtains an output picture signal. The output picture signal is designated with a conversion method selection signal. Information corresponding to the selection signal is loaded from an information memory bank to the coefficient memory and registers.

公开(公告)号：US07852404B2

公开(公告)日：2010-12-14

申请号：US11704045

申请日：2007-02-08

申请人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Kei Hiraizumi ,  Nobuyuki Asakura ,  Takuo Morimura ,  Wataru Niitsuma ,  Takahide Ayata

发明人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Kei Hiraizumi ,  Nobuyuki Asakura ,  Takuo Morimura ,  Wataru Niitsuma ,  Takahide Ayata

IPC分类号： H04N11/20

CPC分类号： G06T3/40 ,  G06T3/4007 ,  H04N7/012 ,  H04N7/0125 ,  H04N7/0137 ,  H04N7/0145

摘要： An information signal processor that is well suitable for use in conversion of an SD signal into an HD signal. The pixel data set corresponding to an objective position in the HD signal is extracted selectively from the SD signal. Class CL to which pixel data set of the objective position belongs is then obtained using the pixel data set. A coefficient production circuit produces coefficient data sets Wi for each class based on coefficient seed data sets and values of picture quality adjusting parameters h and v. A tap selection circuit selectively extracts the data sets xi from the SD signal and then, a calculation circuit produces the pixel data sets of the objective position in the HD signal using the data sets xi and the coefficient data sets Wi. It is thus possible to save on the storage capacity of the memory.

摘要翻译： 一种信号信号处理器，适用于将SD信号转换成HD信号。 从SD信号中选择性地提取与HD信号中的目标位置对应的像素数据集。 然后使用像素数据集来获得目标位置所属的像素数据集所属的CL类。 系数生成电路根据系数种子数据集和图像质量调整参数h，v生成各类的系数数据集Wi，抽头选择电路从SD信号中选择性地提取数据集xi，然后计算电路产生 使用数据集xi和系数数据集Wi的HD信号中的目标位置的像素数据集。 因此可以节省存储器的存储容量。

公开(公告)号：US20100002774A1

公开(公告)日：2010-01-07

申请号：US12559212

申请日：2009-09-14

申请人： Tetsujiro KONDO ,  Wataru NIITSUMA ,  Naoki KOBAYASHI

发明人： Tetsujiro KONDO ,  Wataru NIITSUMA ,  Naoki KOBAYASHI

IPC分类号： H04N7/26

CPC分类号： H04N5/145 ,  G06T7/231 ,  G06T2200/28 ,  G06T2207/10016 ,  G11C7/1006 ,  G11C11/565 ,  H04N19/43 ,  H04N19/436 ,  H04N19/51 ,  H04N19/61

摘要： This invention relates to a memory device and the like that are preferably applied to a case where motion vector is detected using a block matching. Pixel data of a first frame (a reference frame) is stored in a unit A of memory cell array portion 20a in straight binary format. Pixel data of a second frame (a search frame) is stored in a unit B of memory cell array portion 20b in two's complement format. The units A and B have a plurality of memory cells, respectively. Word lines WL related to the pixel data of the first and second frames are simultaneously activated so that charges accumulated in capacitors of each of the memory cells can be combined along one bit line BL. A/D converter 53 outputs a digital signal (absolute difference value) having a value that corresponds to a total amount of charges. When reading the pixel data, a subtraction and a conversion into the absolute difference value are simultaneously performed.

摘要翻译： 本发明涉及优选地应用于使用块匹配检测运动矢量的情况的存储器件等。 第一帧（参考帧）的像素数据以直二进制格式存储在存储单元阵列部分20a的单元A中。 第二帧（搜索帧）的像素数据以二进制格式存储在存储单元阵列部分20b的单元B中。 单元A和B分别具有多个存储单元。 与第一和第二帧的像素数据相关的字线WL被同时激活，使得可以沿着一个位线BL组合每个存储器单元的电容器中积累的电荷。 A / D转换器53输出具有与总电荷量对应的值的数字信号（绝对差值）。 当读取像素数据时，同时执行减法和转换成绝对差值。

公开(公告)号：US07551230B2

公开(公告)日：2009-06-23

申请号：US11197187

申请日：2005-08-04

申请人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Takuo Morimura ,  Nobuyuki Asakura ,  Wataru Niitsuma ,  Kei Hiraizumi ,  Takahide Ayata

发明人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Takuo Morimura ,  Nobuyuki Asakura ,  Wataru Niitsuma ,  Kei Hiraizumi ,  Takahide Ayata

IPC分类号： H04N7/01

CPC分类号： H04N7/0137 ,  G06T3/40 ,  G09G2340/0407 ,  H04N7/0125 ,  H04N7/0145

摘要： The present invention relates to an information signal processor and the like preferable for use in the case of converting a format of an image signal or converting an image size. An input image signal Vin (525i signal) is converted into an output image signal Vout (such as 1080i signal, XGA signal, or 525i signal for obtaining an image to be displayed in a different magnification). A class code CL is obtained from tap data selectively extracted from the Vin and corresponding to each pixel (pixel at a target position) within a unit pixel block, which constitutes Vout. A coefficient production circuit 136 produces coefficient data for each class, which is used at the time of calculating the pixel data at the target position, based on the coefficient seed data for each class and position information h, v about the target position generated in a position information generation circuit 139. A calculation circuit 127 provides pixel data y1 to yp of the target position according to the estimated equation using the tap data xi corresponding to the target position and the coefficient data Wi corresponding to the class code CL.

摘要翻译： 本发明涉及一种信息信号处理器等，其优选用于转换图像信号的格式或转换图像大小的情况。 输入图像信号Vin（525i信号）被转换成输出图像信号Vout（诸如1080i信号，XGA信号或525i信号，用于获得以不同放大率显示的图像）。 根据构成Vout的单位像素块内的每个像素（目标位置的像素），从有选择地从Vin中提取的抽头数据获得类码CL。 系数生成电路136基于每个等级的系数种子数据以及关于在目标位置生成的目标位置的位置信息h，v，在计算目标位置处的像素数据时使用的每个类别的系数数据 位置信息生成电路139.计算电路127使用与目标位置对应的抽头数据xi和与类代码CL对应的系数数据Wi，根据推定的方程，提供目标位置的像素数据y1〜yp。

公开(公告)号：US07397512B2

公开(公告)日：2008-07-08

申请号：US11056141

申请日：2005-02-10

申请人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Nobuyuki Asakura ,  Masashi Uchida ,  Takuo Morimura ,  Kazutaka Ando ,  Hideo Nakaya ,  Tsutomu Watanabe ,  Satoshi Inoue ,  Wataru Niitsuma

发明人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Nobuyuki Asakura ,  Masashi Uchida ,  Takuo Morimura ,  Kazutaka Ando ,  Hideo Nakaya ,  Tsutomu Watanabe ,  Satoshi Inoue ,  Wataru Niitsuma

IPC分类号： H04N5/45

CPC分类号： H04N7/012 ,  H04N7/0125 ,  H04N7/0137 ,  H04N7/0145

摘要： A picture information converting apparatus for generating a plurality of output picture signals. The apparatus includes first data selecting means; second data selecting means; memory means for storing a pre-obtained estimation expression coefficient; pixel value generating means for generating the first pixel with the second pixels selected by the first data selecting means and a linear estimation expression of the estimation expression coefficient; class determining means for generating class information corresponding to the third pixels selected by the second data selecting means and supplying the estimation expression coefficient to the pixel value generating means corresponding to the class information; scanning line structure converting means, connected to the pixel value generating means, for converting a conversion picture to a designated scanning line structure; and controlling means for receiving a control signal that designates a scanning line structure of the output picture signal and for switching over at least one of the estimation expression coefficient, the second pixels selected by the first data selecting means and the third pixels selected by the second data selecting means, corresponding to the control signal.

摘要翻译： 一种用于产生多个输出图像信号的图像信息转换装置。 该装置包括第一数据选择装置; 第二数据选择装置; 用于存储预先获得的估计表达系数的存储装置; 像素值产生装置，用于产生具有由第一数据选择装置选择的第二像素的第一像素和估计表达式系数的线性估计表达式; 类别确定装置，用于产生与由第二数据选择装置选择的第三像素相对应的类别信息，并将估计表达式系数提供给与类信息相对应的像素值产生装置; 扫描线结构转换装置，连接到像素值产生装置，用于将转换图像转换成指定的扫描线结构; 以及控制装置，用于接收指定输出图像信号的扫描线结构的控制信号，并且用于切换估计表达式系数中的至少一个，由第一数据选择装置选择的第二像素和由第二数据选择装置选择的第三像素 数据选择装置，对应于控制信号。

公开(公告)号：US07113225B2

公开(公告)日：2006-09-26

申请号：US10177285

申请日：2002-06-20

申请人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Nobuyuki Asakura ,  Masashi Uchida ,  Takuo Morimura ,  Kazutaka Ando ,  Hideo Nakaya ,  Tsutomu Watanabe ,  Satoshi Inoue ,  Wataru Niitsuma

发明人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Nobuyuki Asakura ,  Masashi Uchida ,  Takuo Morimura ,  Kazutaka Ando ,  Hideo Nakaya ,  Tsutomu Watanabe ,  Satoshi Inoue ,  Wataru Niitsuma

IPC分类号： H04N5/14

CPC分类号： H04N7/012 ,  H04N7/0125 ,  H04N7/0137 ,  H04N7/0145

摘要： A 525i (interlace) signal can be converted into a 1050i signal or a 525p (progressive) signal. A calculating circuit generates pixels of an output picture signal with a linear estimation expression of predictive taps received from a tap selecting circuit and a coefficient received from a coefficient memory. The coefficient memory stores coefficients pre-obtained for individual classes. A class is determined by combining a spatial class corresponding to spatial class taps received from a tap selecting circuit and motion class taps received from a tap selecting circuit. A line sequential converting circuit converts a scanning line structure of an output signal of the calculating circuit 34 and obtains an output picture signal. The output picture signal is designated with a conversion method selection signal. Information corresponding to the selection signal is loaded from an information memory bank to the coefficient memory and registers.

公开(公告)号：US20050162550A1

公开(公告)日：2005-07-28

申请号：US11056141

申请日：2005-02-10

申请人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Nobuyuki Asakura ,  Masashi Uchida ,  Takuo Morimura ,  Kazutaka Ando ,  Hideo Nakaya ,  Tsutomu Watanabe ,  Satoshi Inoue ,  Wataru Niitsuma

发明人： Tetsujiro Kondo ,  Yasushi Tatehira ,  Nobuyuki Asakura ,  Masashi Uchida ,  Takuo Morimura ,  Kazutaka Ando ,  Hideo Nakaya ,  Tsutomu Watanabe ,  Satoshi Inoue ,  Wataru Niitsuma

IPC分类号： H04N5/14 ,  H04N5/46 ,  H04N7/01 ,  H04N5/45 ,  H04N11/20

CPC分类号： H04N7/012 ,  H04N7/0125 ,  H04N7/0137 ,  H04N7/0145

摘要： A picture information converting apparatus for generating a plurality of output picture signals. The apparatus includes first data selecting means; second data selecting means; memory means for storing a pre-obtained estimation expression coefficient; pixel value generating means for generating the first pixel with the second pixels selected by the first data selecting means and a linear estimation expression of the estimation expression coefficient; class determining means for generating class information corresponding to the third pixels selected by the second data selecting means and supplying the estimation expression coefficient to the pixel value generating means corresponding to the class information; scanning line structure converting means, connected to the pixel value generating means, for converting a conversion picture to a designated scanning line structure; and controlling means for receiving a control signal that designates a scanning line structure of the output picture signal and for switching over at least one of the estimation expression coefficient, the second pixels selected by the first data selecting means and the third pixels selected by the second data selecting means, corresponding to the control signal.

摘要翻译： 一种用于产生多个输出图像信号的图像信息转换装置。 该装置包括第一数据选择装置; 第二数据选择装置; 用于存储预先获得的估计表达系数的存储装置; 像素值产生装置，用于产生具有由第一数据选择装置选择的第二像素的第一像素和估计表达式系数的线性估计表达式; 类别确定装置，用于产生与由第二数据选择装置选择的第三像素相对应的类别信息，并将估计表达式系数提供给与类信息相对应的像素值产生装置; 扫描线结构转换装置，连接到像素值产生装置，用于将转换图像转换成指定的扫描线结构; 以及控制装置，用于接收指定输出图像信号的扫描线结构的控制信号，并且用于切换估计表达式系数中的至少一个，由第一数据选择装置选择的第二像素和由第二数据选择装置选择的第三像素 数据选择装置，对应于控制信号。