公开(公告)号：US08323990B2

公开(公告)日：2012-12-04

申请号：US11728184

申请日：2007-03-22

申请人： Wen Shi ,  Wei Wei Ruan

发明人： Wen Shi ,  Wei Wei Ruan

IPC分类号： G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An embodiment of a testing structure in accordance with the present invention comprises at least two segments of a different metal layer through via structures. Each segment includes nodes configured to receive force and sense voltages. Selective application of force and sense voltages to these nodes allows rapid and precise detection of stress-induced immigration in each of the metal layers.

摘要翻译： 根据本发明的实施例涉及允许在多个互连金属化层中测试应力诱导的电迁移的结构和方法。 根据本发明的测试结构的实施例包括通过通孔结构的不同金属层的至少两个段。 每个段包括被配置为接收力和感测电压的节点。 对这些节点的力和感应电压的选择性应用允许在每个金属层中快速和精确地检测应力诱导的移植。

公开(公告)号：US20090033354A1

公开(公告)日：2009-02-05

申请号：US12211615

申请日：2008-09-16

申请人： Wen Shi ,  Wei Wei Ruan

发明人： Wen Shi ,  Wei Wei Ruan

IPC分类号： G01R31/26 ,  H01L23/58

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2884 ,  H01L22/32 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： Multi-purpose poly edge test structure. According to an embodiment, the present invention provides a test structure. The test structure includes a doped silicon substrate, the doped silicon substrate being grounded, the doped silicon substrate including a first gate structure and a second gate structure, the first and second gate structures overlaying the doped silicon substrate. The test structure also includes a first conducting pad being electrically coupled to the first gate structure. The test structure also includes a second conducting pad being electrically coupled to the second gate structure.

摘要翻译： 多功能多边测试结构。 根据实施例，本发明提供一种测试结构。 测试结构包括掺杂硅衬底，掺杂硅衬底接地，掺杂硅衬底包括第一栅极结构和第二栅极结构，第一和第二栅极结构覆盖掺杂硅衬底。 测试结构还包括电耦合到第一栅极结构的第一导电焊盘。 测试结构还包括电耦合到第二栅极结构的第二导电焊盘。

公开(公告)号：US07439538B2

公开(公告)日：2008-10-21

申请号：US11728050

申请日：2007-03-22

申请人： Wen Shi ,  Wei Wei Ruan

发明人： Wen Shi ,  Wei Wei Ruan

IPC分类号： H01L23/58

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2884 ,  H01L22/32 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure in accordance with the present invention allows for testing of both Vbd TDDB, and leakage current between adjacent gate features. The test structure comprises a plurality of parallel polysilicon gate structures overlying a substrate. Traces placing alternate gates in electrical communication with a polysilicon edge are connected by a fuse. In one embodiment, a potential difference is applied across all gates to trigger Vbd, and then the fuse is broken to allow individual probing of breakdown of the alternate groups of gates. In another embodiment, the fuse is broken and then force and sense voltages are applied to the edge polysilicon in communication with the alternate gate groupings, allowing detection of leakage current between the alternate groupings of gates that reveals the existence of an unwanted polysilicon extrusion or bridge.

摘要翻译： 根据本发明的测试结构允许测试两个V DBD TDDB和相邻门特征之间的漏电流。 测试结构包括覆盖在衬底上的多个平行多晶硅栅极结构。 将替代栅极与多晶硅边缘电连接的迹线通过保险丝连接。 在一个实施例中，跨所有门施加电位差以触发V BAT，然后熔断器被破坏以允许单独探测另一组栅极的击穿。 在另一个实施例中，保险丝断开，然后将强制和感测电压施加到与备用栅极分组连通的边缘多晶硅，允许检测在栅极的交替分组之间的泄漏电流，其显示存在不需要的多晶硅挤出或桥 。

公开(公告)号：US20080128692A1

公开(公告)日：2008-06-05

申请号：US11728050

申请日：2007-03-22

申请人： Wen Shi ,  Wei Wei Ruan

发明人： Wen Shi ,  Wei Wei Ruan

IPC分类号： G01R31/26 ,  H01L23/58

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2884 ,  H01L22/32 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure in accordance with the present invention allows for testing of both Vbd TDDB, and leakage current between adjacent gate features. The test structure comprises a plurality of parallel polysilicon gate structures overlying a substrate. Traces placing alternate gates in electrical communication with a polysilicon edge are connected by a fuse. In one embodiment, a potential difference is applied across all gates to trigger Vbd, and then the fuse is broken to allow individual probing of breakdown of the alternate groups of gates. In another embodiment, the fuse is broken and then force and sense voltages are applied to the edge polysilicon in communication with the alternate gate groupings, allowing detection of leakage current between the alternate groupings of gates that reveals the existence of an unwanted polysilicon extrusion or bridge.

公开(公告)号：US08164091B2

公开(公告)日：2012-04-24

申请号：US12211615

申请日：2008-09-16

申请人： Wen Shi ,  Wei Wei Ruan

发明人： Wen Shi ,  Wei Wei Ruan

IPC分类号： H01L23/58

CPC分类号： G01R31/2648 ,  G01R31/2621 ,  G01R31/2884 ,  H01L22/32 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： Multi-purpose poly edge test structure. According to an embodiment, the present invention provides a test structure. The test structure includes a doped silicon substrate, the doped silicon substrate being grounded, the doped silicon substrate including a first gate structure and a second gate structure, the first and second gate structures overlaying the doped silicon substrate. The test structure also includes a first conducting pad being electrically coupled to the first gate structure. The test structure also includes a second conducting pad being electrically coupled to the second gate structure.

摘要翻译： 多功能多边测试结构。 根据实施例，本发明提供一种测试结构。 测试结构包括掺杂硅衬底，掺杂硅衬底接地，掺杂硅衬底包括第一栅极结构和第二栅极结构，第一和第二栅极结构覆盖掺杂硅衬底。 测试结构还包括电耦合到第一栅极结构的第一导电焊盘。 测试结构还包括电耦合到第二栅极结构的第二导电焊盘。

公开(公告)号：US20110074459A1

公开(公告)日：2011-03-31

申请号：US12887491

申请日：2010-09-21

申请人： Wei Wei Ruan ,  Bin Gong ,  Wen Shi

发明人： Wei Wei Ruan ,  Bin Gong ,  Wen Shi

IPC分类号： G01R31/26 ,  H01L23/48

CPC分类号： G01R31/2858 ,  G01R31/2884 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of a test structure in accordance with the present invention comprises a pair of interdigitated comb portions of a metallization layer present in a recess of an inter-layer dielectric (ILD) formed over a polysilicon heater element. A third portion of the metallization layer comprises a serpentine metal line interposed between the comb portions. Application of force voltages, and detection of sense voltages, at various nodes of the metallization portions allows identification of the following: (1) electromigration of metal in the metallization portions; (2) extrusion of metal from one metallization portion to contact another; (3) breakdown voltage (Vbd) and time dependent dielectric breakdown (TDDB) of the ILD; (4) contamination in the metallization portions with mobile ions; and (5) k valve and drift in k value of the ILD. A bias voltage may be applied to the polysilicon heater to accomplish temperature control during testing.

摘要翻译： 根据本发明的测试结构的实施例包括存在于在多晶硅加热器元件上形成的层间电介质（ILD）的凹部中的金属化层的一对叉指梳状部分。 金属化层的第三部分包括插入在梳部之间的蛇形金属线。 在金属化部分的各个节点施加力电压和检测电压允许识别以下内容：（1）金属化部分中金属的电迁移; （2）从一个金属化部分挤出金属以接触另一个; （3）ILD的击穿电压（Vbd）和时间依赖介电击穿（TDDB）; （4）金属化部分用流动离子污染; 和（5）k阀门和ILD的k值漂移。 可以将偏置电压施加到多晶硅加热器以在测试期间实现温度控制。

公开(公告)号：US20080128693A1

公开(公告)日：2008-06-05

申请号：US11728184

申请日：2007-03-22

申请人： Wen Shi ,  Wei Wei Ruan

发明人： Wen Shi ,  Wei Wei Ruan

IPC分类号： H01L23/544 ,  H01L21/66 ,  H01L21/768

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments in accordance with the present invention relate to structures and methods allowing stress-induced electromigration to be tested in multiple interconnect metallization layers. An embodiment of a testing structure in accordance with the present invention comprises at least two segments of a different metal layer through via structures. Each segment includes nodes configured to receive force and sense voltages. Selective application of force and sense voltages to these nodes allows rapid and precise detection of stress-induced immigration in each of the metal layers.

摘要翻译： 根据本发明的实施例涉及允许在多个互连金属化层中测试应力诱导的电迁移的结构和方法。 根据本发明的测试结构的实施例包括通过通孔结构的不同金属层的至少两个段。 每个段包括被配置为接收力和感测电压的节点。 对这些节点的力和感应电压的选择性应用允许在每个金属层中快速和精确地检测应力诱导的移植。