公开(公告)号：US07941713B2

公开(公告)日：2011-05-10

申请号：US12198949

申请日：2008-08-27

Applicant: Chingwen Chang ,  Wei-Chia Cheng ,  Shih-Chieh Lin

Inventor： Chingwen Chang ,  Wei-Chia Cheng ,  Shih-Chieh Lin

IPC: G11C29/00

CPC classification number: G11C29/16 ,  G11C2029/3602

Abstract: A system that provides large instruction sets for testing memory yet reduces area overhead is disclosed. The system for testing a memory of an integrated circuit comprises a set of registers providing element based programmability for a plurality of tests, wherein each test includes a plurality of test elements; a finite state machine for receiving a plurality of test instructions from the set of registers, wherein the finite state machine dispatches signals instructing a test pattern generator to generate a test pattern; a memory control module for applying the generated test pattern to the memory; and a comparator module for comparing a response received from the memory to a stored, known response.

Abstract translation: 公开了一种提供用于测试存储器的大指令集并减少区域开销的系统。 用于测试集成电路的存储器的系统包括一组寄存器，用于为多个测试提供基于元素的可编程性，其中每个测试包括多个测试元件; 用于从该组寄存器接收多个测试指令的有限状态机，其中所述有限状态机器调度指示测试模式发生器产生测试模式的信号; 存储器控制模块，用于将生成的测试图案应用于存储器; 以及用于将从存储器接收的响应与存储的已知响应进行比较的比较器模块。

公开(公告)号：US20080126901A1

公开(公告)日：2008-05-29

申请号：US11563459

申请日：2006-11-27

Applicant: Wei-Chia Cheng ,  Chen-Hui Hsieh

Inventor： Wei-Chia Cheng ,  Chen-Hui Hsieh

IPC: G01R31/28

CPC classification number: G11C29/26 ,  G01R31/31724 ,  G01R31/3187 ,  G11C2029/2602

Abstract: An integrated circuit device includes an embedded memory having a plurality of memory macros and a built-in-self-test (BIST) circuit coupled to the plurality of memory macros for simultaneous operation of the memory macros, wherein the BIST circuit is configured to select from the memory macros' data outputs an individual memory macro's data output for analysis while the memory macros are operated simultaneously.

Abstract translation: 集成电路装置包括具有多个存储器宏的嵌入式存储器和耦合到多个存储器宏的内置自检（BIST）电路，用于同时操作存储器宏，其中BIST电路被配置为选择 从内存宏数据输出一个单独的内存宏的数据输出用于分析，而内存宏同时运行。

公开(公告)号：US07499519B1

公开(公告)日：2009-03-03

申请号：US11954640

申请日：2007-12-12

Applicant: Chen-Hui Hsieh ,  Chingwen Chang ,  Wei-Chia Cheng ,  Shih-Chieh Lin

Inventor： Chen-Hui Hsieh ,  Chingwen Chang ,  Wei-Chia Cheng ,  Shih-Chieh Lin

IPC: G11C19/00

CPC classification number: G11C19/00 ,  G11C19/28

Abstract: A bidirectional shift register is disclosed which comprises a first and second flip-flop, a first multiplexer having an output coupled to an input of the first flip-flop, and a second multiplexer having an output coupled to an input of the second flip-flop wherein an output of the first flip-flop is coupled to an input of the second multiplexer, an output of the second flip-flop is coupled to an input of the first multiplexer.

Abstract translation: 公开了一种双向移位寄存器，其包括第一和第二触发器，具有耦合到第一触发器的输入的输出的第一多路复用器，以及耦合到第二触发器的输入的第二多路复用器 其中所述第一触发器的输出耦合到所述第二多路复用器的输入，所述第二触发器的输出耦合到所述第一多路复用器的输入。

公开(公告)号：US07356434B2

公开(公告)日：2008-04-08

申请号：US11127451

申请日：2005-05-12

Applicant: Jeremy Wu ,  Yu Jen Chen ,  Huan An Wu ,  Wei-Chia Cheng

Inventor： Jeremy Wu ,  Yu Jen Chen ,  Huan An Wu ,  Wei-Chia Cheng

IPC: G06F19/00

CPC classification number: G11C5/066

Abstract: This invention discloses a method of specifying pin states for a memory chip having one or more pins. In one embodiment of the invention, the pins are prioritized to obtain a pin order, wherein the pin state of a pin of a higher order dominates the pin state of a pin of a lower order. A number of possible combinations of the pin states are generated for the pins based on the pin order. The possible combinations are presented using a data presentation format. At least one pin of a higher order dominates at least one pin of a lower order when the at least one pin of a higher order is set in a predetermined pin state, such that the number of the possible combinations presented is reduced by neglecting combinations generated by the pins states of the dominated pins.

Abstract translation: 本发明公开了一种用于指定具有一个或多个引脚的存储器芯片的引脚状态的方法。 在本发明的一个实施例中，优先考虑引脚以获得引脚顺序，其中较高级别的引脚的引脚状态主导低级引脚的引脚状态。 根据引脚顺序为引脚产生引脚状态的多种可能的组合。 可能的组合使用数据呈现格式呈现。 当高阶的至少一个引脚被设置在预定的引脚状态时，至少一个较高级的引脚占优势的至少一个引脚，使得通过忽略所产生的组合来减少呈现的可能组合的数量 由主导引脚的引脚状态。

公开(公告)号：US20100058126A1

公开(公告)日：2010-03-04

申请号：US12198949

申请日：2008-08-27

Applicant: Chingwen Chang ,  Wei-Chia Cheng ,  Shih-Chieh Lin

Inventor： Chingwen Chang ,  Wei-Chia Cheng ,  Shih-Chieh Lin

IPC: G11C29/04 ,  G06F11/22

CPC classification number: G11C29/16 ,  G11C2029/3602

Abstract: A system that provides large instruction sets for testing memory yet reduces area overhead is disclosed. The system for testing a memory of an integrated circuit comprises a set of registers providing element based programmability for a plurality of tests, wherein each test includes a plurality of test elements; a finite state machine for receiving a plurality of test instructions from the set of registers, wherein the finite state machine dispatches signals instructing a test pattern generator to generate a test pattern; a memory control module for applying the generated test pattern to the memory; and a comparator module for comparing a response received from the memory to a stored, known response.

Abstract translation: 公开了一种提供用于测试存储器的大指令集并减少区域开销的系统。 用于测试集成电路的存储器的系统包括一组寄存器，用于为多个测试提供基于元素的可编程性，其中每个测试包括多个测试元件; 用于从该组寄存器接收多个测试指令的有限状态机，其中所述有限状态机器调度指示测试模式发生器产生测试模式的信号; 存储器控制模块，用于将生成的测试图案应用于存储器; 以及用于将从存储器接收的响应与存储的已知响应进行比较的比较器模块。

公开(公告)号：US07656726B2

公开(公告)日：2010-02-02

申请号：US11563459

申请日：2006-11-27

Applicant: Wei-Chia Cheng ,  Chen-Hui Hsieh

Inventor： Wei-Chia Cheng ,  Chen-Hui Hsieh

IPC: G11C29/00

CPC classification number: G11C29/26 ,  G01R31/31724 ,  G01R31/3187 ,  G11C2029/2602

Abstract: An integrated circuit device includes an embedded memory having a plurality of memory macros and a built-in-self-test (BIST) circuit coupled to the plurality of memory macros for simultaneous operation of the memory macros, wherein the BIST circuit is configured to select from the memory macros' data outputs an individual memory macro's data output for analysis while the memory macros are operated simultaneously.

Abstract translation: 集成电路装置包括具有多个存储器宏的嵌入式存储器和耦合到多个存储器宏的内置自检（BIST）电路，用于同时操作存储器宏，其中BIST电路被配置为选择 从内存宏数据输出一个单独的内存宏的数据输出用于分析，而内存宏同时运行。

公开(公告)号：US20060256602A1

公开(公告)日：2006-11-16

申请号：US11127451

申请日：2005-05-12

Applicant: Jeremy Wu ,  Yu Chen ,  Huan Wu ,  Wei-chia Cheng

Inventor： Jeremy Wu ,  Yu Chen ,  Huan Wu ,  Wei-chia Cheng

IPC: G11C5/02

CPC classification number: G11C5/066

Abstract: This invention discloses a method of specifying pin states for a memory chip having one or more pins. In one embodiment of the invention, the pins are prioritized to obtain a pin order, wherein the pin state of a pin of a higher order dominates the pin state of a pin of a lower order. A number of possible combinations of the pin states are generated for the pins based on the pin order. The possible combinations are presented using a data presentation format. At least one pin of a higher order dominates at least one pin of a lower order when the at least one pin of a higher order is set in a predetermined pin state, such that the number of the possible combinations presented is reduced by neglecting combinations generated by the pins states of the dominated pins.

Abstract translation: 本发明公开了一种用于指定具有一个或多个引脚的存储器芯片的引脚状态的方法。 在本发明的一个实施例中，优先考虑引脚以获得引脚顺序，其中较高级别的引脚的引脚状态主导低级引脚的引脚状态。 根据引脚顺序为引脚产生引脚状态的多种可能的组合。 可能的组合使用数据呈现格式呈现。 当高阶的至少一个引脚被设置在预定的引脚状态时，至少一个较高的引脚占优势的至少一个引脚，使得通过忽略所产生的组合来减少呈现的可能组合的数量 由主导引脚的引脚状态。