公开(公告)号：US08334198B2

公开(公告)日：2012-12-18

申请号：US13085029

申请日：2011-04-12

申请人： Jian-Hao Chen ,  Wei-Yang Lee ,  Wei-Yeh Tang ,  Xiong-Fei Yu ,  Kuang-Yuan Hsu

发明人： Jian-Hao Chen ,  Wei-Yang Lee ,  Wei-Yeh Tang ,  Xiong-Fei Yu ,  Kuang-Yuan Hsu

IPC分类号： H01L21/4763

CPC分类号： H01L29/6659 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/7833

摘要： The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及具有多个栅极结构的半导体器件。 制造多个栅极结构的示例性方法包括提供硅衬底; 在衬底上沉积虚拟氧化物层; 在虚拟氧化物层上沉积虚拟栅电极层; 图案化层以限定多个虚拟门; 在所述多个虚拟栅极上形成含氮侧壁间隔物; 在所述含氮侧壁间隔件之间形成层间电介质层; 通过原子层沉积（ALD）工艺在层间介质层上选择性地沉积硬掩模层; 去除虚拟栅极电极层; 去除虚拟氧化物层; 沉积栅极电介质; 并沉积栅电极。

公开(公告)号：US20120264281A1

公开(公告)日：2012-10-18

申请号：US13085029

申请日：2011-04-12

申请人： Jian-Hao CHEN ,  Wei-Yang LEE ,  Wei-Yeh TANG ,  Xiong-Fei YU ,  Kuang-Yuan HSU

发明人： Jian-Hao CHEN ,  Wei-Yang LEE ,  Wei-Yeh TANG ,  Xiong-Fei YU ,  Kuang-Yuan HSU

IPC分类号： H01L21/28

CPC分类号： H01L29/6659 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/7833

摘要： The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with a plurality of gate structures. An exemplary method of fabricating the plurality of gate structures comprises providing a silicon substrate; depositing a dummy oxide layer over the substrate; depositing a dummy gate electrode layer over the dummy oxide layer; patterning the layers to define a plurality of dummy gates; forming nitrogen-containing sidewall spacers on the plurality of dummy gates; forming an interlayer dielectric layer between the nitrogen-containing sidewall spacers; selectively depositing a hard mask layer on the interlayer dielectric layer by an atomic layer deposition (ALD) process; removing the dummy gate electrode layer; removing the dummy oxide layer; depositing a gate dielectric; and depositing a gate electrode.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及具有多个栅极结构的半导体器件。 制造多个栅极结构的示例性方法包括提供硅衬底; 在衬底上沉积虚拟氧化物层; 在虚拟氧化物层上沉积虚拟栅电极层; 图案化层以限定多个虚拟门; 在所述多个虚拟栅极上形成含氮侧壁间隔物; 在所述含氮侧壁间隔件之间形成层间电介质层; 通过原子层沉积（ALD）工艺在层间介质层上选择性地沉积硬掩模层; 去除所述伪栅电极层; 去除虚拟氧化物层; 沉积栅极电介质; 并沉积栅电极。