公开(公告)号：US20240282709A1

公开(公告)日：2024-08-22

申请号：US18112564

申请日：2023-02-22

Applicant: Applied Materials, Inc.

Inventor： Zhaoxuan WANG ,  Jianxin LEI ,  Wenting HOU ,  David Maxwell GAGE ,  Zihao HE

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768

CPC classification number: H01L23/53266 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02381 ,  H01L21/02414 ,  H01L21/02631 ,  H01L21/32051 ,  H01L21/3212 ,  H01L21/76834 ,  H01L21/7684 ,  H01L23/5329

Abstract: A method to produce a layered substrate includes depositing a ruthenium layer having a first average grain size on a substrate; annealing the substrate at a temperature and for a period of time sufficient to produce an annealed ruthenium layer having a second average grain size which is greater than the first average grain size; and removing a portion of the ruthenium layer by chemical mechanical planarization to form a planarized ruthenium layer, to produce the layered substrate. A layered substrate is also disclosed.

公开(公告)号：US20240266417A1

公开(公告)日：2024-08-08

申请号：US18635461

申请日：2024-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsing Hsu ,  Sai-Hooi Yeong ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L29/51 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/516 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/517

Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

公开(公告)号：US20240243010A1

公开(公告)日：2024-07-18

申请号：US18403204

申请日：2024-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIHYUN LEE ,  EUN HYEA KO ,  SOYOUNG LEE ,  THANH CUONG NGUYEN ,  HOON HAN ,  BYUNGKEUN HWANG ,  HIROYUKI UCHIUZOU ,  KIYOSHI MURATA ,  TOMOHARU YOSHINO ,  YOUNJOUNG CHO

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/76831 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02301 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/76844

Abstract: An inhibitor for selectively depositing a thin film may include a compound represented by Formula 1 below:




where, R1 is an aldehyde group, an amino group, a carbonyl group, a ketone group, a nitrile group, an acyl halide group, a substituted or unsubstituted C2 to C20 alkenyl group, or a substituted or unsubstituted C2 to C20 alkynyl group, R2 is a halogen atom, a substituted or unsubstituted C1 to C10 alkylhalide group, a substituted or unsubstituted C4 to C10 tertiary alkyl group, or a substituted or unsubstituted C1 to C10 alkylthio group, and n is an integer from 1 to 5. The inhibitor is adsorbed to a surface of a first layer but not adsorbed to a surface of a second layer. The first layer may include a metal-based material, and the second layer is different from the first layer and may include an insulating material.

公开(公告)号：US11984315B2

公开(公告)日：2024-05-14

申请号：US17227905

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Marcus Johannes Henricus van Dal ,  Peter Ramvall

IPC: H01L29/00 ,  H01L21/02 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L21/02181 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02483 ,  H01L21/02614 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/786

Abstract: Structures and methods of forming the same are provided. A structure according to the present disclosure includes an interconnect structure, an aluminum oxide layer over the interconnect structure, and a transistor formed over the aluminum oxide layer. The transistor includes cuprous oxide.

公开(公告)号：US20240153771A1

公开(公告)日：2024-05-09

申请号：US18313355

申请日：2023-05-07

Applicant: SHIN-ETSU CHEMICAL CO., LTD.

Inventor： Naoki KOBAYASHI ,  Daisuke KORI ,  Hironori SATOH ,  Toshiharu YANO

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/0332 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02255 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31056 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144

Abstract: The present invention is a composition for forming a metal oxide film, including: (A) a metal oxide nanoparticle; (B) a flowability accelerator containing a resin having a structural unit represented by the following general formula (1); (C) a dispersion stabilizer having two or more benzene rings or having one benzene ring and a structure represented by the following general formula (C-1), and the dispersion stabilizer being composed of an aromatic group-containing compound having a molecular weight of 500 or less; and (D) an organic solvent, wherein the flowability accelerator (B) has a content of 9 mass % or more in an entirety of the composition, a ratio Mw/Mn of 2.50≤Mw/Mn≤9.00, and the flowability accelerator (B) having no cardo structure. Thus, there can be provided a composition for forming a metal oxide film that has excellent dry etching resistance compared with a conventional organic underlayer film material, that has excellent filling property compared with a conventional metal hard mask, that can reduce cracking with forming a thick film, and that has excellent storage stability;

公开(公告)号：US20240105447A1

公开(公告)日：2024-03-28

申请号：US18476597

申请日：2023-09-28

Applicant: NEXPERIA B.V.

Inventor： Hans-Juergen Funke ,  Ivan Shiu ,  Tim Böttcher

IPC: H01L21/02 ,  H01L23/498

CPC classification number: H01L21/0228 ,  H01L21/02118 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02282 ,  H01L23/49894

Abstract: The present disclosure relates to a method of improving semiconductor package creepage. The package includes a semiconductor device, and a plurality of electrically conductive contacts at a surface of the package, the package includes insulating material for electrically insulating the package between the plurality of electrically conductive contacts and an initial creepage distance is defined by the shortest distance over the surface of the package between two of the plurality of contacts, and the method includes the steps of: applying a layer of insulating material over at least part of at least one of the two contacts, the insulating material is applied in a thin layer and selected to obtain a package thermal resistance increase less than a factor 3 as compared to an uncoated semiconductor package, to increase the initial creepage distance and improve package creepage of the semiconductor package.

公开(公告)号：US20240097009A1

公开(公告)日：2024-03-21

申请号：US18522064

申请日：2023-11-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chandrashekhar P. SAVANT ,  Tien-Wei YU ,  Ke-Chih LIU ,  Chia-Ming TSAI

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02186 ,  H01L21/0228 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, a channel region, a gate structure, and source/drain regions. The channel region is over the substrate. The gate structure is over the channel region, and includes a high-k dielectric layer, a tungsten layer over the high-k dielectric layer, and a fluorine-containing work function layer over the tungsten layer. The source/drain regions are at opposite sides of the channel region.

公开(公告)号：US11935926B2

公开(公告)日：2024-03-19

申请号：US18156355

申请日：2023-01-18

Applicant: SK hynix Inc.

Inventor： Hyeng-Woo Eom ,  Jung-Myoung Shim ,  Young-Ho Yang ,  Kwang-Wook Lee ,  Won-Joon Choi

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3205 ,  H01L29/51 ,  H10B43/27

CPC classification number: H01L29/40117 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02186 ,  H01L21/02244 ,  H01L21/28568 ,  H01L21/32051 ,  H01L29/513 ,  H10B43/27 ,  H01L21/02178

Abstract: A method for fabricating a semiconductor device includes forming a stack structure including a horizontal recess over a substrate, forming a blocking layer lining the horizontal recess, forming an interface control layer including a dielectric barrier element and a conductive barrier element over the blocking layer, and forming a conductive layer over the interface control layer to fill the horizontal recess.

公开(公告)号：US20240087899A1

公开(公告)日：2024-03-14

申请号：US17941557

申请日：2022-09-09

Applicant: Applied Materials, Inc.

Inventor： Zhihui Liu ,  Seshadri Ganguli ,  Tianyi Huang ,  Yixiong Yang ,  Srinivas Gandikota ,  Yuanhua Zheng ,  Yongjing Lin ,  Keyur Karandikar ,  Elizabeth Mao

IPC: H01L21/225 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L21/225 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0234 ,  H01L29/401

Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. The methods include treating a surface of a metal gate stack with a radical treatment. The radical treatment may be used to treat one or more layers or surfaces of layers in the metal gate stack. The radical treatment may be performed once or multiple times during the methods described herein. The radical treatment comprises flowing one or more of nitrogen radicals (N2*) and hydrogen radicals (H*) over the surface of the metal gate stack.

公开(公告)号：US11923192B2

公开(公告)日：2024-03-05

申请号：US17943336

申请日：2022-09-13

Applicant: ASM IP Holding B.V.

Inventor： Fu Tang ,  Delphine Longrie ,  Peng-Fu Hsu

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/455

CPC classification number: H01L21/0228 ,  C23C16/401 ,  C23C16/45553 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192

Abstract: A method for depositing an oxide film on a substrate by a cyclical deposition is disclosed. The method may include: depositing a metal oxide film over the substrate utilizing at least one deposition cycle of a first sub-cycle of the cyclical deposition process; and depositing a silicon oxide film directly on the metal oxide film utilizing at least one deposition cycle of a second sub-cycle of the cyclical deposition process. Semiconductor device structures including an oxide film deposited by the methods of the disclosure are also disclosed.