公开(公告)号：US5429990A

公开(公告)日：1995-07-04

申请号：US224701

申请日：1994-04-08

申请人： Ming-Tsung Liu ,  Jeffrey Wang ,  Wen Yang Chen ,  D. Y. Wu

发明人： Ming-Tsung Liu ,  Jeffrey Wang ,  Wen Yang Chen ,  D. Y. Wu

IPC分类号： H01L21/768 ,  H01L21/316

CPC分类号： H01L21/76819

摘要： A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via A first silicon oxide layer is deposited over the metal layer. This is covered with a spin-on-glass layer. This layer is dried by baking. The spin-on-glass layer is now fully cured. The cured spin-on-glass layer is now ion implanted under the conditions of between about 1E15 to 1E17 atoms/cm.sup.2 and energy between about 50 to 100 KeV. A silicon oxide layer is deposited thereover. Via openings are now made through the silicon oxide layers and the spin-on-glass layer and filled with metal. This results in excellent planarity with no poisoned via problems. Most importantly, this method can be used for submicron technologies having conductor lines which are spaced from one another by submicron feature size and can be processed without the use of an etch-back process for the cured spin on and glass layer.

摘要翻译： 实现了一种平面化集成电路的新方法。 集成电路的导电层之间的电介质层通过第一氧化硅层沉积在金属层上而形成并平坦化。 这被覆盖了旋涂玻璃层。 该层通过烘烤干燥。 旋涂玻璃层现已完全固化。 固化的旋涂玻璃层现在在约1E15至1E17原子/ cm2之间的条件下离子注入，约为50至100KeV之间的能量。 氧化硅层沉积在其上。 通孔开口现在通过氧化硅层和旋涂玻璃层制成并填充金属。 这导致非常平坦的，无中毒的问题。 最重要的是，该方法可以用于具有通过亚微米特征尺寸彼此分开的导线的亚微米技术，并且可以在不使用用于固化的旋涂和玻璃层的回蚀工艺的情况下进行处理。