公开(公告)号：US12058851B2

公开(公告)日：2024-08-06

申请号：US18199346

申请日：2023-05-18

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Hsu-Yang Wang ,  Chun-Chieh Chiu ,  Shih-Fang Tzou

IPC: H01L21/48 ,  H01L21/768 ,  H10B12/00

CPC classification number: H10B12/485 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76895 ,  H10B12/053 ,  H10B12/482

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

公开(公告)号：US12027495B2

公开(公告)日：2024-07-02

申请号：US17316044

申请日：2021-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kun Sil Lee ,  Dong Kwan Kim

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/76804 ,  H01L21/76819 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L25/50 ,  H01L21/7685 ,  H01L23/315 ,  H01L24/81 ,  H01L2221/101 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2225/06548

Abstract: A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via.

公开(公告)号：US12022666B2

公开(公告)日：2024-06-25

申请号：US17534953

申请日：2021-11-24

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Andrew Leslie Beemer

IPC: H10B63/00 ,  H01L21/321 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/80 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H10N70/231 ,  H10N70/826 ,  H10N70/841 ,  H10N70/882

Abstract: Methods, systems, and devices for via formation in a memory device are described. A memory cell stack for a memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A via may also be formed in an area outside of the memory array, and the via may protrude from a material that surrounds the via. A material may then be formed above the memory cell stack and also above the via, and the top surface of the barrier material may be planarized until at least a portion of the via is exposed. A subsequently formed material may thereby be in direct contact with the top of the via, while a portion of the initially formed material may remain above the memory cell stack.

公开(公告)号：US11942424B2

公开(公告)日：2024-03-26

申请号：US17457048

申请日：2021-12-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Ruilong Xie ,  Tsung-Sheng Kang ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/762 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76819 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/5329 ,  H01L21/7682 ,  H01L23/5222

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.

公开(公告)号：US11883926B2

公开(公告)日：2024-01-30

申请号：US17319637

申请日：2021-05-13

Applicant: Kioxia Corporation

Inventor： Takahiko Kawasaki ,  Yukiteru Matsui ,  Akifumi Gawase

IPC: B24B37/26 ,  B24B37/24 ,  B24B53/017 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3105 ,  H01L23/532

CPC classification number: B24B37/26 ,  B24B37/24 ,  B24B53/017 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76895 ,  H01L23/53257

Abstract: A polishing pad is described. The polishing pad includes a surface having plural recess portions, and a substrate is polished by the surface. In the pad, an average width of the recess portions at one area of the surface in a direction parallel to the surface is 20 μm or less, and an average density of the recess portions at one area of the surface is 1,300/mm2 or more.

公开(公告)号：US20230369494A1

公开(公告)日：2023-11-16

申请号：US18357797

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： CHUN-NENG LIN ,  JIAN-JOU LIAN ,  MING-HSI YEH

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/28

CPC classification number: H01L29/785 ,  H01L29/7834 ,  H01L29/66795 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/41791 ,  H01L29/66545 ,  H01L21/823437 ,  H01L21/28247 ,  H01L21/823431 ,  H01L29/6656 ,  H01L21/76819

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.

公开(公告)号：US20230352405A1

公开(公告)日：2023-11-02

申请号：US17820949

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Janggeun Lee ,  Jaemyung Choi ,  Wonhyuk Hong ,  Kang-ill Seo

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L21/76819 ,  H01L23/53295 ,  H01L23/53228 ,  H01L23/53257

Abstract: Integrated circuit devices are provided. An integrated circuit device includes a first insulating layer and a metal via that is in the first insulating layer. The integrated circuit device includes a second insulating layer on the first insulating layer. The integrated circuit device includes a conductive material that is between sidewalls of the second insulating layer and on the metal via. Moreover, the integrated circuit device includes a metal line that is on the conductive material and/or the second insulating layer. Related methods of forming integrated circuit devices are also provided.

公开(公告)号：US11804403B2

公开(公告)日：2023-10-31

申请号：US17382379

申请日：2021-07-22

Applicant: United Semiconductor (Xiamen) Co., Ltd.

Inventor： Ji He Huang ,  Wen Yi Tan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76819 ,  H01L21/76835 ,  H01L23/5283 ,  H01L23/53295

Abstract: A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.

公开(公告)号：US11798847B2

公开(公告)日：2023-10-24

申请号：US17117727

申请日：2020-12-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Osamu Koike ,  Yutaka Kadogawa

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/762 ,  H01L27/146 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L21/76898 ,  H01L21/76224 ,  H01L21/76819 ,  H01L23/481 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76229 ,  H01L27/14636 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05548 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2225/06541

Abstract: There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.

公开(公告)号：US20230332017A1

公开(公告)日：2023-10-19

申请号：US18297260

申请日：2023-04-07

Applicant: SK enpulse Co., Ltd.

Inventor： Seung Chul HONG ,  Kangsik MYUNG ,  Han Teo PARK ,  Deok Su HAN ,  Yongsoo CHOI

IPC: H01L21/768 ,  C09G1/02

CPC classification number: C09G1/02 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76898

Abstract: A composition for semiconductor processing includes abrasive particles, and a dishing control additive, comprising a first dishing control additive and a second dishing control additive. The first dishing control additive includes a compound having a betaine group and a salicylic group or a derivative thereof, and the second dishing control additive includes an azole-based compound. The first dishing control additive includes 0.07 parts by weight or more based on 100 parts by weight of the abrasive particles, and the second dishing control additive includes 0.13 parts by weight or less based on 100 parts by weight of the abrasive particles.