System and methods for evaluating inferences of unknown attributes in a social network
    1.
    发明授权
    System and methods for evaluating inferences of unknown attributes in a social network 有权
    用于评估社交网络中未知属性的推论的系统和方法

    公开(公告)号:US08160993B2

    公开(公告)日:2012-04-17

    申请号:US12124640

    申请日:2008-05-21

    IPC分类号: G06N5/04

    CPC分类号: G06F21/6245

    摘要: A method and system for determining a probability of inferring an unknown attribute value for an attribute of interest for a target node in a social network. The method comprises the steps of receiving as an input attribute values and link relationships for a plurality of additional nodes in the social network, creating a simplified network using the input values and relationships, and calculating the probability of inferring the unknown attribute value for the target node.

    摘要翻译: 一种用于确定为社交网络中的目标节点感兴趣的属性推断未知属性值的概率的方法和系统。 该方法包括以下步骤:接收用于社交网络中的多个附加节点的输入属性值和链接关系,使用输入值和关系创建简化网络,以及计算推断目标的未知属性值的概率 节点。

    Database system with query relaxation using type abstraction hierarchy
(TAH) as query condition relaxation structure
    2.
    发明授权
    Database system with query relaxation using type abstraction hierarchy (TAH) as query condition relaxation structure 失效
    使用类型抽象层次(TAH)作为查询条件松弛结构的查询放松的数据库系统

    公开(公告)号:US5956707A

    公开(公告)日:1999-09-21

    申请号:US800035

    申请日:1997-02-13

    申请人: Wesley W. Chu

    发明人: Wesley W. Chu

    IPC分类号: G06F17/30

    摘要: A system for obtaining target data from a conventional computer database in response to an input query which has at least one attribute includes a Type Abstraction Hierarchy (TAH) manager for providing a TAH structure including relaxation conditions for said at least one attribute. A control unit successively applies a database query which corresponds to the input query to and receives data from the database, with progressively relaxed conditions of the attribute(s) being provided by the TAH manager, until the target data in the form of a specified number of ranked answers which satisfy the attribute conditions is obtained. The attribute relaxation process can be controlled such as relaxation order, preference list, reject, etc. to obtain user and context specific answers. The system can produce approximate answers or answers to query with conceptual terms. The input query can including cooperative operators such as "APPROXIMATELY", "NEAR TO" or "SIMILAR TO" or conceptual terms (e.g. "long"), which the conventional database is not capable of directly processing. The control unit converts the cooperative operators and conceptual terms into database operator which the database is capable of processing. The TAH structure includes TAHs having leaves corresponding to instances of the attributes respectively, and a hierarchical arrangement of nodes that specify ranges which include at least one of the instances respectively. The instances can be numerical and/or non-numerical. The nodes can be defined by conceptual names (terms) that describe the instances under that node (e.g. dark color, long runway).

    摘要翻译: 用于响应于具有至少一个属性的输入查询从常规计算机数据库获得目标数据的系统包括用于提供包括所述至少一个属性的松弛条件的TAH结构的类型抽象层次结构(TAH)管理器。 一个控制单元连续地将与输入查询对应的数据库查询应用于数据库中并从TAH管理器提供的逐渐放宽的属性状态,直到以指定数字形式的目标数据为止 获得满足属性条件的排名答案。 可以控制属性松弛过程,例如放松顺序,偏好列表,拒绝等,以获得用户和上下文的具体答案。 该系统可以用概念术语产生大致的答案或答案。 输入查询可以包括常规数据库不能直接处理的诸如“近似”,“近似”或“类似TO”或概念术语(例如“长”)的协作运算符。 控制单元将合作运算符和概念术语转换为数据库能够处理的数据库运算符。 TAH结构包括分别具有与属性实例相对应的叶子的TAH,以及分别指定包括至少一个实例的范围的节点的分层布置。 实例可以是数字和/或非数值的。 可以通过描述该节点下的实例(例如深色,长跑道)的概念名称(术语)来定义节点。

    Database event detection and notification system using type abstraction hierarchy (TAH)
    3.
    发明授权
    Database event detection and notification system using type abstraction hierarchy (TAH) 失效
    使用类型抽象层次(TAH)的数据库事件检测和通知系统

    公开(公告)号:US06427146B1

    公开(公告)日:2002-07-30

    申请号:US09539799

    申请日:2000-03-31

    申请人: Wesley W. Chu

    发明人: Wesley W. Chu

    IPC分类号: G06F1730

    摘要: A database event detection and notification system includes a rule definer for defining a high level rule which can include conceptual terms (e.g. bad, heavy) and as cooperative operators (e.g. approximate, similar-to, near-to). A rule converter converts the high level rule into a low level rule in which the conceptual terms and cooperative operators are quantified. An event manager detects and evaluates an event generated by the database or a Local Event Detector (LED). A rule manager applies the low level rule to the event detected by the event manager, and an action manager performs an action in accordance with the application of the rule by the rule manager. The action can include notifying a specified person or program that the event has occurred. The rule converter and the action manager utilize a Type Abstraction Hierarchy (TAH) for converting the high level rule into the low level rule and performing the action respectively. The rule comprises an attribute. The TAH comprises leaves corresponding to instances of the attribute, and a hierarchical arrangement of nodes which specify ranges that include at least one of the instances respectively. The rule converter and the action manager are configured to convert the high level rule into the low level rule and perform the action by relaxing a value of the attribute in accordance with the TAH. An existing rule can be modified or a new rule inserted into the system without shutting down the system and recompiling all the rules.

    摘要翻译: 数据库事件检测和通知系统包括用于定义高级规则的规则定义器,其可以包括概念术语(例如,坏的,重的)和作为协作操作符(例如,近似,类似于,靠近)。 规则转换器将高级规则转换成低级规则,其中概念术语和合作操作符被量化。 事件管理器检测并评估由数据库或本地事件检测器(LED)生成的事件。 规则管理器将低级规则应用于事件管理器检测到的事件,并且操作管理器根据规则管理器应用规则执行操作。 该操作可以包括通知指定的人员或程序事件已发生。 规则转换器和动作管理器利用类型抽象层次结构(TAH)将高级规则转换为低级规则并分别执行动作。 该规则包括一个属性。 TAH包括与属性实例相对应的叶,以及分别指定包括至少一个实例的范围的节点的分层排列。 规则转换器和动作管理器被配置为将高级规则转换成低级规则,并通过根据TAH放宽属性的值来执行动作。 可以修改现有规则或将新规则插入到系统中,而不必关闭系统并重新编译所有规则。

    System and method for retrieving scenario-specific documents
    4.
    发明授权
    System and method for retrieving scenario-specific documents 有权
    用于检索场景特定文档的系统和方法

    公开(公告)号:US07548910B1

    公开(公告)日:2009-06-16

    申请号:US11045717

    申请日:2005-01-28

    IPC分类号: G06F17/03

    摘要: A system and method for automatically extracting relevant key concepts from a free-text document and indexing the document using the extracted key concepts. The indexing mechanism applies syntactic and semantic filters to filter out irrelevant terms. The remaining terms are deemed to be key concepts for the free-text document. An input search query is compared against the key concepts extracted for the free-text document for determining whether the document satisfies the query. Prior to applying the search query, additional scenario-specific terms are added to the search query in order to improve retrieval performance. The query expansion mechanism generates a list of candidate expansion concepts, filters the list of candidate expansion concepts based on a user-entered scenario concept, and expands the input query based on the candidate expansion concepts remaining after the filtering process.

    摘要翻译: 一种用于从自由文本文档自动提取相关关键概念并使用提取的关键概念索引文档的系统和方法。 索引机制应用语法和语义过滤器来过滤不相关的术语。 其余条款被认为是自由文本文件的关键概念。 将输入搜索查询与为自由文本文档提取的关键概念进行比较,以确定文档是否满足查询。 在应用搜索查询之前,为了提高检索性能,可以向搜索查询添加附加的场景特定术语。 查询扩展机制生成候选扩展概念列表,根据用户输入的方案概念过滤候选扩展概念列表,并根据过滤后剩余的候选扩展概念扩展输入查询。

    Multi-access memory module for data processing systems
    5.
    发明授权
    Multi-access memory module for data processing systems 失效
    用于数据处理系统的多存取内存模块

    公开(公告)号:US4104719A

    公开(公告)日:1978-08-01

    申请号:US687977

    申请日:1976-05-20

    CPC分类号: G11C11/418 G11C8/16

    摘要: Memory apparatus for use in a data processing system and which includes ints entirety a number of multi-access modules each formed of a plurality of data bit cells. Each module is accessed through multiple independent channels and each channel is capable of servicing a different request during the same memory cycle. Structurally, each independent channel is coupled by a drive line to a data bit storage cell and each drive line is energizable to close a switch mechanism for connecting a read-write bit line circuit to the cell. Individual cells have their own independent bit line circuits and switch mechanisms. Thus, plural requests for a read-out of a single cell can be serviced simultaneously. Special circuitry is suggested for resolving conflicts arising in situations involving simultaneous read-write or write requests addressed to a single cell.

    摘要翻译: 用于数据处理系统的存储装置,其全部包括多个由多个数据位单元构成的多址模块。 每个模块通过多个独立通道进行访问,每个通道能够在同一个内存周期内处理不同的请求。 在结构上,每个独立通道通过驱动线耦合到数据位存储单元,并且每个驱动线可通电以闭合用于将读写位线电路连接到单元的开关机构。 单个单元具有它们自己的独立位线电路和开关机构。 因此,可以同时维护对单个单元的读出的多个请求。 建议使用特殊电路来解决在同时读取单个单元的写入或写入请求的情况下产生的冲突。

    Statistical multiplexing system for computer communications

    公开(公告)号:US4093823A

    公开(公告)日:1978-06-06

    申请号:US812802

    申请日:1977-07-05

    申请人: Wesley W. Chu

    发明人: Wesley W. Chu

    IPC分类号: G06F13/38 H04J3/24 H04J3/16

    CPC分类号: H04J3/24 G06F13/385

    摘要: A statistical multiplexing system is provided for computer communications, in which asynchronous user messages are transmitted from the individual terminals to the central processor, or other remote location, in random order. The messages are statistically multiplexed, with time slots being assigned in the communication channel as each message is received from the terminals, and with no time slots being assigned for idle periods, which greatly increases channel utilization. A buffer memory is required in the system to temporarily store messages from the terminals at statistical peaks. To improve channel efficiency, several characters for the same terminal may be collected together in the system to form an addressed data sub-block so as to reduce address label requirements. These sub-blocks are assembled into multiplexed data blocks by a microprocessor and stored in the buffer memory. To relieve the microprocessor load, data blocks are transferred from the memory to the transmitter via a direct memory access facility for transmission over the communication channel to the desired destinations. Input rejection controls are provided to avoid overflow of the buffer memory. A demultiplexer is provided in the system which handles multiplexed data blocks received from the remote location and which transfers the received blocks under the control of the microprocessor to the buffer memory by way of the direct memory access facility. The microprocessor initiates positive and negative acknowledgment signals which are sent to the remote location, and it then demultiplexes the correctly received multiplexed data blocks and transfers them to the appropriate output terminal interfaces for distribution to the terminals. The multiplexer is capable of multiplexing messages from both asynchronous and synchronous input terminals. The microprocessor schedules and multiplexes data blocks from synchronous terminals and from asynchronous terminals over the common communication channel to one or more remote locations.

    Statistical multiplexing system for computer communications
    7.
    发明授权
    Statistical multiplexing system for computer communications 失效
    用于计算机通信的统计多路复用系统

    公开(公告)号:US4082922A

    公开(公告)日:1978-04-04

    申请号:US770672

    申请日:1977-02-22

    申请人: Wesley W. Chu

    发明人: Wesley W. Chu

    IPC分类号: H04J3/24 H04J6/00

    CPC分类号: H04J3/24

    摘要: A statistical multiplexing system is provided which includes two microprocessors with independent local memories, the microprocessors being designated as the "send microprocessor" and the "receive microprocessor," respectively. Communication between the two microprocessors is provided by an interprocess communication facility which comprises a first-in-first-out memory, and such communication is initiated by interrupt signals to the respective microprocessors. The send microprocessor assembles characters from different terminals, echos characters back to the different terminals in accordance with a local echoing function, collects characters from the same terminal into data sub-blocks with block time-out interrupts, multiplexes the data sub-blocks, forms the data sub-blocks into data blocks and transmits the data blocks to remote stations according to data destination addresses in the data blocks. The receive microprocessor handles received multiplexed data blocks and initiates positive and negative acknowledgment signals; and it then demultiplexes the correctly received multiplexed data blocks and passes them on to the appropriate output terminals.

    SYSTEM AND METHODS FOR EVALUATING INFERENCES OF UNKNOWN ATTRIBUTES IN A SOCIAL NETWORK
    8.
    发明申请
    SYSTEM AND METHODS FOR EVALUATING INFERENCES OF UNKNOWN ATTRIBUTES IN A SOCIAL NETWORK 有权
    用于评估社会网络中未知属性感染的系统和方法

    公开(公告)号:US20080294589A1

    公开(公告)日:2008-11-27

    申请号:US12124640

    申请日:2008-05-21

    IPC分类号: G06N5/04

    CPC分类号: G06F21/6245

    摘要: A method and system for determining a probability of inferring an unknown attribute value for an attribute of interest for a target node in a social network. The method comprises the steps of receiving as an input attribute values and link relationships for a plurality of additional nodes in the social network, creating a simplified network using the input values and relationships, and calculating the probability of inferring the unknown attribute value for the target node.

    摘要翻译: 一种用于确定为社交网络中的目标节点感兴趣的属性推断未知属性值的概率的方法和系统。 该方法包括以下步骤:接收用于社交网络中的多个附加节点的输入属性值和链接关系,使用输入值和关系创建简化网络,以及计算推断目标的未知属性值的概率 节点。

    Multiplexed MOS multiaccess memory system
    9.
    发明授权
    Multiplexed MOS multiaccess memory system 失效
    多路MOS多处理存储器系统

    公开(公告)号:US4415991A

    公开(公告)日:1983-11-15

    申请号:US276439

    申请日:1981-06-22

    IPC分类号: G11C8/16 G11C13/00

    CPC分类号: G11C8/16

    摘要: Multiaccess memory modules are each connected by means of a bus to a systemddress multiplexer and to a system data multiplexer/demultiplexer. Each module includes a multiaccess memory connected to the system address multiplexer through a component address demultiplexer and a single bus for being addressed. Each multiaccess memory is also connected to the system data multiplexer/demultiplexer through a component data multiplexer/demultiplexer and a single bus for reading or sensing the memory and writing data into the memory. The memory cells of the multiaccess memory components consist of capacitor storage cells, also known as metal oxide silicon (semiconductor) (MOS) capacitors.

    摘要翻译: 多处理存储器模块各自通过总线连接到系统地址多路复用器和系统数据多路复用器/解复用器。 每个模块包括通过分量地址解复用器连接到系统地址多路复用器的多路存储器和用于寻址的单个总线。 每个多处理存储器还通过组件数据多路复用器/解复用器和用于读取或感测存储器并将数据写入存储器的单个总线连接到系统数据多路复用器/解复用器。 多处理存储器组件的存储单元由电容器存储单元组成,也称为金属氧化物硅(半导体)(MOS)电容器。