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公开(公告)号：US06473131B1
公开(公告)日：2002-10-29
申请号：US09607492
申请日：2000-06-30
IPC分类号： H03M112
CPC分类号： H03M1/1255 , G09G5/008 , H04L7/0083 , H04L7/0334
摘要： A system includes a signal reconstruction controller (110) electrically coupled to at least one analog-to-digital converter (ADC) (112) and to a phase adjustable clock source (108). A sampling clock signal (116) is electrically coupled from the clock source (108) to the at least one ADC (112). The at least one ADC (112) samples an electronic signal according to the sampling clock signal (116) to provide a digital representation of the electronic signal. The controller (110) samples data from the ADC (112) at different sampling points in the electronic signal and determines the edges (140) of the electronic signal and the noisy samples (142, 144) that are away from the edges (140) of the electronic signal. By finding the least noisy sample (146, 148) that is away from the edges (140) of the electronic signal the controller (110) adjusts the phase of a sampling signal clock (116) to a sampling point that is the most reliable to sample the electronic signal to provide a digital representation thereof.
摘要翻译： 系统包括电耦合到至少一个模数转换器（ADC）（112）和相位可调时钟源（108）的信号重构控制器（110）。 采样时钟信号（116）从时钟源（108）电耦合到至少一个ADC（112）。 至少一个ADC（112）根据采样时钟信号（116）采样电子信号，以提供电子信号的数字表示。 控制器（110）在电子信号中的不同采样点处从ADC（112）采样数据，并确定电子信号的边缘（140）和远离边缘（140）的噪声样本（142,144） 的电子信号。 通过找到远离电子信号的边缘（140）的噪声最小的样本（146,148），控制器（110）将采样信号时钟（116）的相位调整到最可靠的采样点 对电子信号进行采样以提供其数字表示。
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2.发明授权Cascaded integrator comb filter with arbitrary integer decimation value and scaling for unity gain 失效具有任意整数抽取值和单位增益缩放的级联积分梳状滤波器公开(公告)号：US07102548B1
公开(公告)日：2006-09-05
申请号：US11219415
申请日：2005-09-02
申请人： Shenq-Huey Wang , William D. Elliott , Xiemei Meng
发明人： Shenq-Huey Wang , William D. Elliott , Xiemei Meng
CPC分类号： H03H17/0671 , H03H2017/0678
摘要： We disclose a CIC digital filter having an arbitrary-integer decimation rate. The filter has a shifter connected to its input. The shifter receives a shift control input, where the shift control input is pre-computed as equal to the integer portion of 2 raised to the base-2 logarithm of the gain of the CIC filter. There is a multiplier connected between the input and the shifter. In other embodiments, the multiplier could be connected between the input and the shifter. Sequentially-connected integrator functions are connected to the shifter (or multiplier); a decimation function receives input from the integrator functions; and sequentially-connected differentiator functions receive input from the decimation function. The decimation function has a selectable rate equal to any integer between 1 and a number equal to the predetermined maximum decimation value. The multiplier is configured to compute the product of each input data sample by a correction factor; the correction factor being pre-computed as equal to the fractional portion of 2 raised to the base-2 logarithm of the gain of the CIC filter, so as to correct the gain of the CIC filter for decimation values not a power of 2.
摘要翻译： 我们公开了具有任意整数抽取率的CIC数字滤波器。 滤波器具有连接到其输入端的移位器。 移位器接收移位控制输入，其中移位控制输入被预先计算为等于CIC滤波器的增益的基数2对数的2的整数部分。 在输入和移位器之间连接一个乘法器。 在其他实施例中，乘法器可以连接在输入和移位器之间。 顺序连接的积分器功能连接到移位器（或乘法器）; 抽取功能从积分器功能接收输入; 并且顺序连接的微分器功能从抽取功能接收输入。 抽取功能具有等于1和等于预定最大抽取值的数字之间的任何整数的可选择速率。 乘法器被配置为通过校正因子来计算每个输入数据样本的乘积; 校正因子被预先计算为等于2的分数部分提高到CIC滤波器的增益的基数2对数，以便校正CIC滤波器对于不是2的幂的抽取值的增益。
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公开(公告)号：US07348915B2
公开(公告)日：2008-03-25
申请号：US11489226
申请日：2006-07-19
IPC分类号： H03M1/12
CPC分类号： H03H17/0294 , H03H17/06
摘要： An analog-to-digital conversion system has an analog-to-digital converter and a digital-filter system. The digital-filter system is connected to the output of the analog-to-digital converter. A processor is connected to the output of the digital-filter system so that the processor transparently receives filtered sample data in the native format of the analog-to-digital converter. An FIR filter circuit in the digital-filter system is connected to receive data from, and output filtered data to, a sample capture and data-type conversion circuit connected between the analog-to-digital converter and the processor. A configuration and control-register circuit is connected to the circuit for sample collection and data-type conversion, and to the FIR filter circuit, for selectively controlling the operation of the digital filter system according to parameters for data conversion and filter operation passed to the configuration and control-register circuit over a serial interface.
摘要翻译： 模数转换系统具有模数转换器和数字滤波器系统。 数字滤波器系统连接到模数转换器的输出。 处理器连接到数字滤波器系统的输出，使得处理器以模数转换器的本机格式透明地接收滤波后的样本数据。 连接数字滤波器系统中的FIR滤波器电路，以连接在模数转换器和处理器之间的采样捕获和数据类型转换电路接收数据并将滤波后的数据输出到其中。 配置和控制寄存器电路连接到用于采样和数据类型转换的电路，并连接到FIR滤波器电路，用于根据用于数据转换和滤波器操作的参数选择性地控制数字滤波器系统的操作 配置和控制寄存器电路通过串行接口。
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公开(公告)号：US20080018511A1
公开(公告)日：2008-01-24
申请号：US11489226
申请日：2006-07-19
IPC分类号： H03M1/66
CPC分类号： H03H17/0294 , H03H17/06
摘要： An analog-to-digital conversion system has an analog-to-digital converter and a digital-filter system. The digital-filter system is connected to the output of the analog-to-digital converter. A processor is connected to the output of the digital-filter system so that the processor transparently receives filtered sample data in the native format of the analog-to-digital converter. An FIR filter circuit in the digital-filter system is connected to receive data from, and output filtered data to, a sample capture and data-type conversion circuit connected between the analog-to-digital converter and the processor. A configuration and control-register circuit is connected to the circuit for sample collection and data-type conversion, and to the FIR filter circuit, for selectively controlling the operation of the digital filter system according to parameters for data conversion and filter operation passed to the configuration and control-register circuit over a serial interface.
摘要翻译： 模数转换系统具有模数转换器和数字滤波器系统。 数字滤波器系统连接到模数转换器的输出。 处理器连接到数字滤波器系统的输出，使得处理器以模数转换器的本机格式透明地接收滤波后的采样数据。 连接数字滤波器系统中的FIR滤波器电路，以连接在模数转换器和处理器之间的采样捕获和数据类型转换电路接收数据并将滤波后的数据输出到其中。 配置和控制寄存器电路连接到用于采样和数据类型转换的电路，并连接到FIR滤波器电路，用于根据用于数据转换和滤波器操作的参数选择性地控制数字滤波器系统的操作 配置和控制寄存器电路通过串行接口。
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公开(公告)号：US06826247B1
公开(公告)日：2004-11-30
申请号：US09534932
申请日：2000-03-24
IPC分类号： H03D324
CPC分类号： G09G5/008 , H03K5/1252 , H03K5/131 , H03K5/133 , H03K2005/00058 , H03L7/0814 , H03L7/089 , H03L2207/50
摘要： A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal. The digital frequency synthesizer also a non-glitching MUX electrically coupled to the digital DLL for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse glitch-free from the selected output tap, and a phase accumulator electrically coupled to the non-glitching MUX for precisely dividing a timing period of the input reference signal and for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse at a precise point in the timing period from the output tap. The digital phase detector, is electrically coupled to the digital frequency synthesizer to compare an edge of the input reference signal to an edge of a synthesized signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the synthesized signal.
摘要翻译： 系统包括由全数字电路实现和标准单元结构构成的数字锁相环（PLL）。 数字PLL包括数字频率合成器和数字相位检测器。 数字频率合成器包括包括多个延迟链的数字DLL，每个延迟链包括至少一个数字可编程延迟元件，用于配置多个延迟链以实现具有输入参考信号的锁相。 数字频率合成器还是电耦合到数字DLL的非毛刺MUX，用于从至少一个数字可编程延迟元件中的一个选择抽头输出，以从所选择的输出抽头中选择至少一个脉冲毛刺，以及相位 累加器电耦合到非毛刺MUX，用于精确地划分输入参考信号的定时周期并且用于从至少一个数字可编程延迟元件中的一个选择抽头输出以在定时中的精确点处选择至少一个脉冲 期间从输出水龙头。 数字相位检测器电耦合到数字频率合成器，以将输入参考信号的边沿与合成信号的边沿进行比较，以提供表示输入参考信号的边沿与边沿之间的相位误差的数字码信息 的合成信号。
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公开(公告)号：US06628276B1
公开(公告)日：2003-09-30
申请号：US09535049
申请日：2000-03-24
申请人： William D. Elliott
发明人： William D. Elliott
IPC分类号： G09G500
CPC分类号： G09G5/008 , H03L7/0814 , H03L7/085 , H04N5/126 , H04N5/66
摘要： A system includes an integrated circuit device that compares the relative phase of first and second signals to a very high precision. The system includes a first input for receiving the first signal with a first edge, and a second input for receiving the second signal with a second edge. A first delay chain includes a first at least one delay element, and the first signal is delayed across the first at least one delay element, each of the first at least one delay element includes an output tap. A second delay chain includes a second at least one delay element, the second signal is delayed across the second at least one delay element, each of the second at least one delay element includes an output tap. At least one symmetrical Flip-Flop includes a first and second input electrically coupled to an output tap of each of the first and second at least one delay element, respectively, such that an output of each of the at least one Flip-Flop indicates which of the first and second edge arrived first at the respective first and second input of the at least one Flip-Flop.
摘要翻译： 一种系统包括将第一和第二信号的相对相位非常高的精度进行比较的集成电路装置。 该系统包括用于接收具有第一边缘的第一信号的第一输入端和用于用第二边缘接收第二信号的第二输入端。 第一延迟链包括第一至少一个延迟元件，并且第一信号被延迟跨越第一至少一个延迟元件，第一至少一个延迟元件中的每一个包括输出抽头。 第二延迟链包括第二至少一个延迟元件，第二信号被延迟跨越第二至少一个延迟元件，第二至少一个延迟元件中的每一个包括输出抽头。 至少一个对称的触发器包括分别电耦合到第一和第二至少一个延迟元件中的每一个的输出抽头的第一和第二输入，使得至少一个触发器中的每一个的输出指示哪个 的第一和第二边缘首先到达所述至少一个触发器的相应的第一和第二输入。
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