公开(公告)号：US20100321083A1

公开(公告)日：2010-12-23

申请号：US12488767

申请日：2009-06-22

申请人： David J. Chen ,  William F. Lawson ,  David W. Mann

发明人： David J. Chen ,  William F. Lawson ,  David W. Mann

IPC分类号： H03L5/00 ,  H01S4/00

CPC分类号： H03K19/018521 ,  Y10T29/49002

摘要： A voltage level translating circuit that allows low voltage signals to be translated to higher voltages, a design structure utilized in the design, manufacture, and/or testing of the voltage level translating circuit, and a method of manufacturing the voltage level translating circuit are described. The translating circuit utilizes two different voltage domains. The high voltage rail of the low voltage domain acts as the ground of the high voltage domain. The translating circuit also utilizes a voltage buffer electrically connected to the high voltage domain and to the low voltage domain to prevent the circuit devices in either domain from seeing too high of a voltage. The translating circuit allows the circuits after the translating circuit to work with signals utilizing the high voltage rail of the high voltage domain.

摘要翻译： 描述了允许将低电压信号转换为更高电压的电压电平转换电路，在电压电平转换电路的设计，制造和/或测试中使用的设计结构以及制造电压电平转换电路的方法 。 转换电路使用两个不同的电压域。 低电压域的高压轨作为高电压域的接地。 转换电路还利用电连接到高电压域和低电压域的电压缓冲器，以防止任一领域中的电路器件看到太高的电压。 转换电路允许转换电路之后的电路利用高电压域的高电压轨来处理信号。

公开(公告)号：US07355452B2

公开(公告)日：2008-04-08

申请号：US11393343

申请日：2006-03-30

申请人： Michael K. Kerr ,  William F. Lawson

发明人： Michael K. Kerr ,  William F. Lawson

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H04L25/0292 ,  H04L1/243 ,  H04L25/0272

摘要： A high-speed interface between a first network component and a second network component includes a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP). Implementing the high-speed interface calls for applying a bias to the a positive input bus and a negative input bus to periodically multiplex a data signal, thus providing a common receiving path for functional data and wrap data of the data signal.

摘要翻译： 第一网络组件和第二网络组件之间的高速接口包括用于从第一网络组件接收输入数据信号的正电压输入（VINP）和负电压输入（VINN） 通过正输入总线和负输入总线耦合到负输出电路（OUTN）和负电压输入（VINN）的正电压输入（VINP），负电压输入（VINN）也耦合到正输出电路 OUTP）。 实施高速接口要求对正输入总线和负输入总线施加偏置，以周期性地复用数据信号，从而提供用于功能数据的公共接收路径并包裹数据信号的数据。

公开(公告)号：US08766663B2

公开(公告)日：2014-07-01

申请号：US13526004

申请日：2012-06-18

申请人： David J. Chen ,  William F. Lawson

发明人： David J. Chen ,  William F. Lawson

IPC分类号： H03K19/003 ,  G06F17/50

CPC分类号： H03K19/0005

摘要： A method and circuit for implementing calibration of a linearly weighted, thermal coded I/O driver output stage, and a design structure on which the subject circuit resides are provided. The circuit includes a PFET calibration impedance matching function determining calibration PVTP bits for calibrating output stage PFETs of the linearly weighted, thermal coded I/O driver output stage, an NFET calibration impedance matching function determining calibration bits PVTN for calibrating output stage NFETs of the linearly weighted, thermal coded I/O driver output stage once the PFET calibration is complete and an output latch function providing the calibration PVTP and PVTN outputs for the I/O driver output stage to match an impedance of an external calibration resistor. A clock logic function generates an output latch clock and an internal reset signal completing calibration.

摘要翻译： 一种用于实现线性加权的热编码I / O驱动器输出级的校准的方法和电路以及设置有被摄体电路的设计结构。 该电路包括PFET校准阻抗匹配功能，确定用于校准线性加权的热编码I / O驱动器输出级的输出级PFET的校准PVTP位，NFET校准阻抗匹配函数确定用于校准线性的输出级NFET的校准位PVTN 一旦PFET校准完成并且输出锁存功能为I / O驱动器输出级提供校准PVTP和PVTN输出以匹配外部校准电阻器的阻抗，则加权，热编码的I / O驱动器输出级。 时钟逻辑功能产生输出锁存时钟和内部复位信号完成校准。

公开(公告)号：US08704572B2

公开(公告)日：2014-04-22

申请号：US13443183

申请日：2012-04-10

申请人： Michael K. Kerr ,  William F. Lawson

发明人： Michael K. Kerr ,  William F. Lawson

IPC分类号： H03K3/017

CPC分类号： H03K19/018528

摘要： A method and circuit for implementing low duty cycle distortion and low power differential to single ended level shifter, and a design structure on which the subject circuit resides are provided. The circuit includes an input differential amplifier providing positive and negative differential amplifier output signals coupled to an output amplifier providing a single ended output signal. The output amplifier amplifies and inverts the negative differential amplifier output signal. The output amplifier amplifies and superimposes the positive differential amplifier output signal with the amplified and inverted negative differential amplifier output signal, providing the single ended output signal with low duty cycle distortion.

摘要翻译： 一种用于实现低占空比失真和低功率差分到单端电平移位器的方法和电路，以及设置有目标电路所在的设计结构。 该电路包括输入差分放大器，其提供耦合到提供单端输出信号的输出放大器的正和负差分放大器输出信号。 输出放大器放大并反相负差分放大器输出信号。 输出放大器放大并叠加正差分放大器输出信号与放大和反相负差分放大器输出信号，提供具有低占空比失真的单端输出信号。

公开(公告)号：US20130335114A1

公开(公告)日：2013-12-19

申请号：US13526004

申请日：2012-06-18

申请人： David J. Chen ,  William F. Lawson

发明人： David J. Chen ,  William F. Lawson

IPC分类号： H03K19/003 ,  G06F17/50

CPC分类号： H03K19/0005

摘要： A method and circuit for implementing calibration of a linearly weighted, thermal coded I/O driver output stage, and a design structure on which the subject circuit resides are provided. The circuit includes a PFET calibration impedance matching function determining calibration PVTP bits for calibrating output stage PFETs of the linearly weighted, thermal coded I/O driver output stage, an NFET calibration impedance matching function determining calibration bits PVTN for calibrating output stage NFETs of the linearly weighted, thermal coded I/O driver output stage once the PFET calibration is complete and an output latch function providing the calibration PVTP and PVTN outputs for the I/O driver output stage to match an impedance of an external calibration resistor. A clock logic function generates an output latch clock and an internal reset signal completing calibration.

摘要翻译： 一种用于实现线性加权的热编码I / O驱动器输出级的校准的方法和电路以及设置有被摄体电路的设计结构。 该电路包括PFET校准阻抗匹配功能，确定用于校准线性加权的热编码I / O驱动器输出级的输出级PFET的校准PVTP位，NFET校准阻抗匹配函数确定用于校准线性的输出级NFET的校准位PVTN 一旦PFET校准完成并且输出锁存功能为I / O驱动器输出级提供校准PVTP和PVTN输出以匹配外部校准电阻器的阻抗，则加权，热编码的I / O驱动器输出级。 时钟逻辑功能产生输出锁存时钟和内部复位信号完成校准。

公开(公告)号：US20130265091A1

公开(公告)日：2013-10-10

申请号：US13443183

申请日：2012-04-10

申请人： Michael K. Kerr ,  William F. Lawson

发明人： Michael K. Kerr ,  William F. Lawson

IPC分类号： H03K3/017

CPC分类号： H03K19/018528

摘要： A method and circuit for implementing low duty cycle distortion and low power differential to single ended level shifter, and a design structure on which the subject circuit resides are provided. The circuit includes an input differential amplifier providing positive and negative differential amplifier output signals coupled to an output amplifier providing a single ended output signal. The output amplifier amplifies and inverts the negative differential amplifier output signal. The output amplifier amplifies and superimposes the positive differential amplifier output signal with the amplified and inverted negative differential amplifier output signal, providing the single ended output signal with low duty cycle distortion.

摘要翻译： 一种用于实现低占空比失真和低功率差分到单端电平移位器的方法和电路，以及设置有目标电路所在的设计结构。 该电路包括输入差分放大器，其提供耦合到提供单端输出信号的输出放大器的正和负差分放大器输出信号。 输出放大器放大并反相负差分放大器输出信号。 输出放大器放大并叠加正差分放大器输出信号与放大和反相负差分放大器输出信号，提供具有低占空比失真的单端输出信号。

公开(公告)号：US07301386B2

公开(公告)日：2007-11-27

申请号：US11278236

申请日：2006-03-31

申请人： David J. Chen ,  Michael K. Kerr ,  William F. Lawson

发明人： David J. Chen ,  Michael K. Kerr ,  William F. Lawson

IPC分类号： H03L5/00

CPC分类号： H03K19/018521 ,  H03K19/01707

摘要： A voltage level shifting device for translating a lower operating voltage to a higher operating voltage includes a first input node coupled to a first pull down device and a second input node coupled to a second pull down device. The second node receives a complementary logic signal with respect to the first input node, the first and second input nodes associated with the lower operating voltage. A first pull up device is in series with the first pull down device and second pull up device is in series with the second pull down device, with the first and second pull up devices coupled to a power supply at the higher operating voltage. An output node is between the second pull down device and the second pull up device, the output node controlling the conductivity of the first pull up device. A clamping device is in parallel with the first pull up device, and configured to prevent the second pull up device from becoming fully saturated.

摘要翻译： 用于将较低工作电压转换到较高工作电压的电压电平移动装置包括耦合到第一下拉装置的第一输入节点和耦合到第二下拉装置的第二输入节点。 第二节点相对于第一输入节点接收互补逻辑信号，第一和第二输入节点与较低工作电压相关联。 第一上拉装置与第一下拉装置串联，第二上拉装置与第二下拉装置串联，第一和第二上拉装置在较高工作电压下耦合到电源。 输出节点位于第二下拉装置和第二上拉装置之间，输出节点控制第一上拉装置的电导率。 夹紧装置与第一上拉装置并联，并且构造成防止第二拉起装置变得完全饱和。

公开(公告)号：US06636821B2

公开(公告)日：2003-10-21

申请号：US09898252

申请日：2001-07-03

申请人： William F. Lawson

发明人： William F. Lawson

IPC分类号： H03K19003

CPC分类号： H03K19/0005

摘要： An output driver impedance calibration circuit which is used to make I/O (input/output) off chip driver characteristics, for a plurality of output driver circuits, alike on the same chip. The output impedance of an input/output driver circuit is calibrated by providing an external target impedance reference (it could be a multiple of the actual target output impedance), multiple devices in the output stage of the I/O driver circuit, a circuit to determine the value of the actual output impedance as compared with its target output impedance and a determination of when to stop the calibration process.

摘要翻译： 输出驱动器阻抗校准电路，用于对同一芯片上的多个输出驱动器电路进行I / O（输入/输出）芯片驱动器特性。 输入/输出驱动电路的输出阻抗通过提供外部目标阻抗参考（可能是实际目标输出阻抗的倍数），I / O驱动电路的输出级中的多个器件，电路 确定实际输出阻抗的值与其目标输出阻抗相比较，并确定何时停止校准过程。

公开(公告)号：US06262599B1

公开(公告)日：2001-07-17

申请号：US09544132

申请日：2000-04-06

申请人： Terry C. Coughlin, Jr. ,  William F. Lawson ,  Joseph M. Milewski

发明人： Terry C. Coughlin, Jr. ,  William F. Lawson ,  Joseph M. Milewski

IPC分类号： H03K190175

CPC分类号： H03K19/09429 ,  H03K19/018521

摘要： A low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the higher voltage logic level signals. A first predrive stage is provided, comprising buffers (e.g., CMOS inverters) for tuning and balancing the circuit and the core signal combining circuit of a second predrive stage, thereby enabling IC designers to reduce the size of transistors in the level-shifting stage and providing more flexibility in the tuning of the predrive circuitry to synchronize or balance the logical transitions of the complementary transistors of the output driving stage. The invention provides a faster balanced level-shifting output buffer which enables higher frequency operation.

摘要翻译： 低功耗CMOS双向I / O缓冲器，可将低电压核心逻辑电平信号转换为较高电压逻辑电平信号。 提供了第一预驱动级，包括用于调谐和平衡第二预驱动级的电路和核心信号组合电路的缓冲器（例如，CMOS反相器），从而使得IC设计者能够在电平移位级中减小晶体管的尺寸， 在预调制电路的调谐中提供更大的灵活性以同步或平衡输出驱动级的互补晶体管的逻辑转换。 本发明提供了一种更快的平衡电平转换输出缓冲器，其实现更高频率的操作。

公开(公告)号：US08847636B2

公开(公告)日：2014-09-30

申请号：US13443209

申请日：2012-04-10

申请人： Michael K. Kerr ,  William F. Lawson

发明人： Michael K. Kerr ,  William F. Lawson

IPC分类号： H03B1/00 ,  H03K3/00 ,  H03K5/12 ,  H03L5/00

CPC分类号： G06F17/5063 ,  G06F2217/78 ,  H03K19/00315

摘要： A method and circuit for implementing protection for complementary metal oxide semiconductor (CMOS) output drivers, and a design structure on which the subject circuit resides are provided. An output driver stage transistor stack includes a plurality of series connected PFETs series connected with a plurality of series connected NFETs connected between upper and lower voltage supply rails. A pair of offset DC voltage levels provides respective gate voltages of an intermediate PFET and an intermediate NFET in the output driver stage transistor stack. A pair of pre-driver circuits receiving voltage level translated logic signals drive respective gate inputs of the upper PFET and the lower NFET in the output driver stage transistor stack. A voltage feedback circuit provides respective gate voltages of the PFET and NFET connected together in the output driver stage transistor stack.

摘要翻译： 一种用于实现互补金属氧化物半导体（CMOS）输出驱动器的保护的方法和电路，以及设置有该电路所在的设计结构。 输出驱动器级晶体管堆叠包括多个串联连接的PFET，其串联连接在连接在上部和下部电压供应轨道之间的多个串联连接的NFET。 一对偏移DC电压电平在输出驱动级晶体管堆叠中提供中间PFET和中间NFET的相应栅极电压。 接收电压电平转换逻辑信号的一对预驱动器电路驱动输出驱动级晶体管堆叠中的上PFET和下NFET的相应栅极输入。 电压反馈电路提供在输出驱动级晶体管堆叠中连接在一起的PFET和NFET的相应栅极电压。