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公开(公告)号：US06762638B2
公开(公告)日：2004-07-13
申请号：US10065228
申请日：2002-10-16
IPC分类号： H03K3289
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/356008
摘要： A method and a flip-flop is disclosed in which power consumption is reduced in a standby mode. In a first aspect, the flip-flop comprises a first latch adapted to be coupled to a first power supply and a second latch coupled to the first latch and adapted to be coupled to a second power supply. The first and second power supplies are independently controllable to minimize power consumption in a standby mode. In a second aspect, a method for minimizing the power consumption of a flip-flop is also disclosed. The flip-flop includes a first latch and a second latch coupled thereto. The method comprises providing a first independently controllable power supply coupled to the master latch; and providing a second independently controllable power supply coupled to the slave latch. The method further includes reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode.
摘要翻译： 公开了一种在待机模式下功耗降低的方法和触发器。 在第一方面，触发器包括适于耦合到第一电源的第一锁存器和耦合到第一锁存器并适于耦合到第二电源的第二锁存器。 第一和第二电源是可独立控制的，以便在待机模式下最小化功耗。 在第二方面，还公开了一种用于最小化触发器的功耗的方法。 触发器包括第一锁存器和与其耦合的第二锁存器。 该方法包括提供耦合到主锁存器的第一独立可控电源; 以及提供耦合到从锁存器的第二独立可控电源。 该方法还包括响应于省电模式的检测而降低第一和第二电源中的至少一个的电压。
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公开(公告)号：US20130015882A1
公开(公告)日：2013-01-17
申请号：US13180598
申请日：2011-07-12
IPC分类号： H03K19/0175 , H01L21/82
CPC分类号： H01L27/0207 , H03K19/018521
摘要： Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power savings for multi-bit implementation of level shifter design. A two-bit VLS to shift bits from a first voltage level logic to a second voltage level logic. The VLS formed with a first N-well in a substrate. The VLS formed with a second N-well in the substrate, adjacent to a side of the first N-well. The VLS formed with a third N-well in the substrate, adjacent to a side of the first N-well and opposite the second N-well. A first one-bit VLS circuit having a portion formed on the first N-well and a portion formed on the second N-well. A second bit VLS circuit having a portion formed on the first N-well and a portion formed on the third N-well.
摘要翻译： 用于批量CMOS技术中的电压电平转换器（VLS）设计的方法和装置。 一种多电压电路或VLS，可在不同的电压电平下工作，并可为电平移位器设计的多位实现提供面积和功耗。 一个两位VLS，用于将位从第一电压电平逻辑移位到第二电压电平逻辑。 VLS在衬底中形成有第一N阱。 VLS在衬底中形成有第二N阱，邻近第一N阱的一侧。 VLS在衬底中形成有第三N阱，邻近第一N阱的一侧并与第二N阱相对。 第一单位VLS电路，其具有形成在第一N阱上的部分和形成在第二N阱上的部分。 具有形成在第一N阱上的部分和形成在第三N阱上的部分的第二位VLS电路。
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公开(公告)号：US07301384B2
公开(公告)日：2007-11-27
申请号：US11394557
申请日：2006-03-31
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the multimode, uniform-latency CGC generates a pulse clock signal via a clock generation path responsive to a clock chopping signal being active and generates a phase clock signal via the same clock generation path responsive to the clock chopping signal being inactive. The clock chopping signal is activated responsive to a mode control input signal being in a first state and deactivated responsive to either the mode control input signal being in a second state or a plurality of clock enable signals being inactive. In one or more embodiments, a multimode, uniform-latency CGC is included in a microprocessor for providing pulse clock signals to inter-stage pulsed sequential storage elements when operating in a timing sensitive mode and for providing phase clock signals to the inter-stage pulsed sequential storage elements when operating in a timing insensitive mode.
摘要翻译： 本文描述了多模均匀延迟时钟产生电路（CGC）。 在一个示例中，多模均衡延迟CGC响应于时钟斩波信号有效而经由时钟产生通路产生脉冲时钟信号，并且响应于时钟斩波信号无效而经由相同的时钟产生通路产生相位时钟信号。 响应于处于第一状态的模式控制输入信号来激活时钟斩波信号，并且响应于处于第二状态的模式控制输入信号或多个时钟使能信号无效而停止时钟斩波信号。 在一个或多个实施例中，多模均匀延迟CGC被包括在微处理器中，用于当以定时灵敏模式工作时将脉冲时钟信号提供给级间脉冲顺序存储元件，并且用于将相位时钟信号提供给级间脉冲 在时序不敏感模式下运行的顺序存储元件。
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公开(公告)号：US08487658B2
公开(公告)日：2013-07-16
申请号：US13180598
申请日：2011-07-12
CPC分类号： H01L27/0207 , H03K19/018521
摘要： Method and apparatus for voltage level shifters (VLS) design in bulk CMOS technology. A multi-voltage circuit or VLS that operate with different voltage levels and that provides area and power savings for multi-bit implementation of level shifter design. A two-bit VLS to shift bits from a first voltage level logic to a second voltage level logic. The VLS formed with a first N-well in a substrate. The VLS formed with a second N-well in the substrate, adjacent to a side of the first N-well. The VLS formed with a third N-well in the substrate, adjacent to a side of the first N-well and opposite the second N-well. A first one-bit VLS circuit having a portion formed on the first N-well and a portion formed on the second N-well. A second bit VLS circuit having a portion formed on the first N-well and a portion formed on the third N-well.
摘要翻译： 用于批量CMOS技术中的电压电平转换器（VLS）设计的方法和装置。 一种多电压电路或VLS，可在不同的电压电平下工作，并可为电平移位器设计的多位实现提供面积和功耗。 一个两位VLS，用于将位从第一电压电平逻辑移位到第二电压电平逻辑。 VLS在衬底中形成有第一N阱。 VLS在衬底中形成有第二N阱，邻近第一N阱的一侧。 VLS在衬底中形成有第三N阱，邻近第一N阱的一侧并与第二N阱相对。 第一单位VLS电路，其具有形成在第一N阱上的部分和形成在第二N阱上的部分。 具有形成在第一N阱上的部分和形成在第三N阱上的部分的第二位VLS电路。
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5.发明授权Method and apparatus for reducing clock enable setup time in a multi-enabled clock gating circuit 有权用于在多使能时钟选通电路中降低时钟使能建立时间的方法和装置公开(公告)号：US07279935B2
公开(公告)日：2007-10-09
申请号：US11371380
申请日：2006-03-09
IPC分类号： H03K19/00 , H03K19/096
CPC分类号： G06F1/10
摘要： A multi-enabled clock gating circuit reduces clock enable setup time. In one example, the multi-enabled clock gating circuit comprises an OAI logic gate and a clock enable control circuit. The OAI logic gate is configured to generate a gated clock signal by inverting an input clock signal responsive to one of a timing-sensitive clock enable signal and a timing-insensitive clock enable signal being active. The clock enable control circuit is configured to prevent the OAI logic gate from receiving the timing-insensitive clock enable signal responsive to the timing-sensitive clock enable signal being active. In one or more embodiments, a multi-enabled clock gating circuit having reduced clock enable setup time may be included in an integrated circuit for implementing clock gating during different operating modes of the integrated circuit.
摘要翻译： 多使能时钟选通电路可减少时钟使能建立时间。 在一个示例中，多使能时钟门控电路包括OAI逻辑门和时钟使能控制电路。 OAI逻辑门被配置为响应于时钟敏感时钟使能信号和不敏感时钟使能信号中的一个被激活而通过反相输入时钟信号来产生门控时钟信号。 时钟使能控制电路被配置为防止OAI逻辑门响应于时钟敏感时钟使能信号被激活而接收不定时不敏感的时钟使能信号。 在一个或多个实施例中，具有降低的时钟使能建立时间的多使能时钟门控电路可以被包括在用于在集成电路的不同操作模式期间实现时钟门控的集成电路中。
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