公开(公告)号：US20070174805A1

公开(公告)日：2007-07-26

申请号：US11342125

申请日：2006-01-26

申请人： Yu-Chin Hsu ,  Furshing Tsai ,  Wori-Tzy Jong

发明人： Yu-Chin Hsu ,  Furshing Tsai ,  Wori-Tzy Jong

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A register transfer level (RTL) IC design describing a IC as comprising a plurality of logic blocks communicating via signals and using a high level language to describe the logic blocks according to the logical relationships between signals they receive and signals they generate. A computer-aided synthesizer processes an RTL IC design to produce a gate level design for the IC describing its logic blocks as comprising instances of cells communicating via signals. A synthesizer or emulator processes the gate level design to produce a gate level dump file referencing signals of the gate level design and indicating how those signals behave in response to time-varying signals supplied as inputs to the IC. The gate level dump file is converted into an RTL dump file referencing signals of the RTL design and indicating how those signals behave. A debugger processes the RTL dump file to produce displays depicting the RTL design and behavior of signals indicated by the RTL dump file. Thus while the IC is simulated or emulated at the gate level of the design to produce waveform data for a debugger, the gate level-to-RTL dump file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results.

摘要翻译： 一种描述IC的寄存器传送级（RTL）IC设计，其包括通过信号通信的多个逻辑块，并且使用高级语言根据它们接收的信号与它们产生的信号之间的逻辑关系来描述逻辑块。 计算机辅助合成器处理RTL IC设计以产生描述其逻辑块的IC的门级设计，包括通过信号通信的小区的实例。 合成器或仿真器处理门电平设计以产生参考门级设计的信号的栅极电平转储文件，并指示这些信号如何响应于作为IC的输入提供的时变信号而行为。 门级转储文件转换为引用RTL设计信号的RTL转储文件，并指示这些信号的行为。 调试器处理RTL转储文件以产生描绘RTL转换文件指示的信号的RTL设计和行为的显示。 因此，当IC在设计的门级模拟或仿真以产生调试器的波形数据时，门级到RTL转储文件转换过程使得设计者能够根据门级仿真或调试更熟悉的RTL设计， 仿真结果。

公开(公告)号：US07478346B2

公开(公告)日：2009-01-13

申请号：US11342125

申请日：2006-01-26

申请人： Yu-Chin Hsu ,  Furshing Tsai ,  Wori-Tzy Jong

发明人： Yu-Chin Hsu ,  Furshing Tsai ,  Wori-Tzy Jong

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5022

摘要： A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump file is converted into an RTL dump file indicating how signals of the RTL design behave. A debugger processes the RTL dump file to produce displays depicting the RTL design and behavior of signals indicated by the RTL dump file. Thus while the IC is simulated or emulated at the gate level of the design to produce waveform data for a debugger, the gate level-to-RTL dump file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results. file conversion process enables a designer debug the more familiar RTL design based on the gate level simulation or emulation results.

摘要翻译： 合成器或仿真器处理从RTL设计派生的门级IC设计，以产生指示门级设计的信号行为的门级转储文件。 门级转储文件转换为RTL转储文件，指示RTL设计的信号如何运行。 调试器处理RTL转储文件以产生描绘RTL转换文件指示的信号的RTL设计和行为的显示。 因此，当IC在设计的门级模拟或仿真以产生调试器的波形数据时，门级到RTL转储文件转换过程使得设计者能够根据门级仿真或调试更熟悉的RTL设计， 仿真结果。 文件转换过程使设计人员能够根据门级仿真或仿真结果调试更熟悉的RTL设计。