公开(公告)号：US20240264975A1

公开(公告)日：2024-08-08

申请号：US18619382

申请日：2024-03-28

申请人： XDL Technologies Inc.

发明人： Yuan Li ,  Jianbin Zhu

IPC分类号： G06F15/80 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/445 ,  G06F12/0815 ,  G06F13/16 ,  G06F15/78

CPC分类号： G06F15/8023 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/34 ,  G06F9/3808 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/44505 ,  G06F12/0815 ,  G06F13/1673 ,  G06F15/7821 ,  G06F15/7867 ,  G06F15/7871 ,  G06F15/7875 ,  G06F15/7878 ,  G06F15/7885 ,  G06F15/7889 ,  G06F15/8046 ,  G06F15/8061 ,  G06F15/8069 ,  G06F15/8092 ,  G06F2212/1021 ,  Y02D10/00

摘要： Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.