公开(公告)号：US07061777B2

公开(公告)日：2006-06-13

申请号：US10907831

申请日：2005-04-18

申请人： Jianhong Zeng ,  Jianping Ying ,  Xiaojun Deng ,  Xingkuan Guo ,  Aiming Xiong

发明人： Jianhong Zeng ,  Jianping Ying ,  Xiaojun Deng ,  Xingkuan Guo ,  Aiming Xiong

IPC分类号： H02M3/335 ,  H02M7/538

CPC分类号： H02M3/33569 ,  H02M7/487

摘要： An input stage circuit of a three-level DC/DC converter is provided. The input stage circuit uses metal-oxide-semiconductor field effect transistors (MOSFETs) to discharge a flying capacitor to maintain the voltage across the flying capacitor at a half of the input voltage. Not only can the input stage circuit solve the high voltage issue across the flying capacitor in the prior art, but the circuit is able to operate normally without increasing power consumption during discharging, thereby avoiding problems of the prior art.

摘要翻译： 提供三电平DC / DC转换器的输入级电路。 输入级电路使用金属氧化物半导体场效应晶体管（MOSFET）来放电飞跨电容器，以将跨越电容器的电压保持在输入电压的一半。 输入级电路不仅可以解决现有技术中跨越飞溅电容器的高电压问题，而且电路能够正常工作，而不会在放电期间增加功耗，从而避免了现有技术的问题。

公开(公告)号：US20060050537A1

公开(公告)日：2006-03-09

申请号：US10907831

申请日：2005-04-18

申请人： Jianhong Zeng ,  Jianping Ying ,  Xiaojun Deng ,  Xingkuan Guo ,  Aiming Xiong

发明人： Jianhong Zeng ,  Jianping Ying ,  Xiaojun Deng ,  Xingkuan Guo ,  Aiming Xiong

IPC分类号： H02M3/335

CPC分类号： H02M3/33569 ,  H02M7/487

摘要： An input stage circuit of a three-level DC/DC converter is provided. The input stage circuit uses metal-oxide-semiconductor field effect transistors (MOSFETs) to discharge a flying capacitor to maintain the voltage across the flying capacitor at a half of the input voltage. Not only can the input stage circuit solve the high voltage issue across the flying capacitor in the prior art, but the circuit is able to operate normally without increasing power consumption during discharging, thereby avoiding problems of the prior art.

摘要翻译： 提供三电平DC / DC转换器的输入级电路。 输入级电路使用金属氧化物半导体场效应晶体管（MOSFET）来放电飞跨电容器，以将跨越电容器的电压保持在输入电压的一半。 输入级电路不仅可以解决现有技术中跨越飞溅电容器的高电压问题，而且电路能够正常工作，而不会在放电期间增加功耗，从而避免了现有技术的问题。

公开(公告)号：US06593195B1

公开(公告)日：2003-07-15

申请号：US09241271

申请日：1999-02-01

申请人： Xiaojun Deng ,  Isik C. Kizilyalli ,  Stephen C. Kuehne

发明人： Xiaojun Deng ,  Isik C. Kizilyalli ,  Stephen C. Kuehne

IPC分类号： H01L21336

CPC分类号： H01L29/792

摘要： The memory element of the present invention utilizes a substrate, a first conductive connection, a second conductive connection, and an ionic layer. The substrate includes a source region, a drain region, and a channel region, which is disposed between the source region and the drain region. The ionic layer includes ions and is coupled to the substrate. The first connection is coupled to the source region, and the second connection is coupled to the drain region. An electrical field is applied through said ionic layer such that the ions in the ionic layer move. When the memory element is to exhibit a logical high state, the polarity of the electrical field causes the ions to move toward the channel region. This pulls the electrons in the source and drain regions into the channel region making the channel region conductive. When the memory element is to exhibit a logical low state, the polarity of the electrical field causes the ions to move away from the channel region. As a result, the channel region becomes non-conductive, and the first conductive connection is, therefore, insulated from the second conductive connection.

摘要翻译： 本发明的存储元件利用衬底，第一导电连接，第二导电连接和离子层。 衬底包括设置在源极区域和漏极区域之间的源极区域，漏极区域和沟道区域。 离子层包括离子并且耦合到衬底。 第一连接耦合到源极区，并且第二连接耦合到漏极区。 通过所述离子层施加电场，使得离子层中的离子移动。 当存储元件呈现逻辑高状态时，电场的极性导致离子朝向沟道区移动。 这将源极和漏极区域中的电子拉入通道区域，使沟道区域导通。 当存储元件呈现逻辑低状态时，电场的极性使得离子离开沟道区域。 结果，沟道区域变得不导电，因此第一导电连接与第二导电连接绝缘。