公开(公告)号：US08369425B2

公开(公告)日：2013-02-05

申请号：US12054028

申请日：2008-03-24

Applicant: Ziquan Bai ,  Hong Wei Kong ,  Honggang Zhang ,  Ya Jing ,  Xu Zhao ,  Danxun Shen

Inventor： Ziquan Bai ,  Hong Wei Kong ,  Honggang Zhang ,  Ya Jing ,  Xu Zhao ,  Danxun Shen

IPC: H04K1/10

CPC classification number: H04L25/0226 ,  H04L5/0048 ,  H04L27/2613 ,  H04L27/2626 ,  H04L2025/03426

Abstract: An apparatus for archiving robust channel estimation in a communication system includes a training sequence generator to generate a training sequence. A formatter inserts the training sequence to a frame. A transmitting module is employed to transmit the frame. The training sequence generator further includes a symbol generator to generate a plurality of training symbols satisfying a predetermined constraint such that the training symbols are insensitive to synchronization error and a training sequence forming unit that forms the training sequence from the training symbols generated by the training symbol generator.

Abstract translation: 用于在通信系统中归档鲁棒信道估计的装置包括产生训练序列的训练序列发生器。 格式化程序将训练序列插入到一个帧中。 采用发送模块来发送帧。 训练序列生成器还包括符号生成器，用于生成满足预定约束的多个训练符号，使得训练符号对同步误差不敏感，训练序列形成单元从训练符号生成的训练符号形成训练序列 发电机。

公开(公告)号：US08126086B2

公开(公告)日：2012-02-28

申请号：US12023135

申请日：2008-01-31

Applicant: Ziquan Bai ,  Hongwei Kong ,  Ya Jing

Inventor： Ziquan Bai ,  Hongwei Kong ,  Ya Jing

IPC: H04B17/00

CPC classification number: H04L27/3863 ,  H04L25/0204 ,  H04L27/2647 ,  H04L2025/03414 ,  H04L2025/03426 ,  H04L2027/0016

Abstract: A system for determining in-phase and quadrature-phase mismatch in a multiple-input, multiple-output (MIMO) communication architecture includes at least one transmitter coupled to at least one receiver and an in-phase (I) signal, quadrature-phase (Q) signal mismatch element configured to receive and Q signal components over at least one communication channel, the I/Q signal mismatch element also configured to provide a signal representing gain imbalance, a signal representing quadrature error and a signal representing I/Q offset.

Abstract translation: 用于确定多输入多输出（MIMO）通信架构中的同相和正交相位失配的系统包括耦合到至少一个接收机的至少一个发射机和同相（I）信号，正交相位 （Q）信号失配元件，被配置为通过至少一个通信信道接收和Q信号分量，所述I / Q信号失配元件还被配置为提供表示增益不平衡的信号，表示正交误差的信号和表示I / Q偏移的信号 。

公开(公告)号：US20090196334A1

公开(公告)日：2009-08-06

申请号：US12023135

申请日：2008-01-31

Applicant: Ziquan Bai ,  Hongwei Kong ,  Ya Jing

Inventor： Ziquan Bai ,  Hongwei Kong ,  Ya Jing

IPC: H04B17/00

CPC classification number: H04L27/3863 ,  H04L25/0204 ,  H04L27/2647 ,  H04L2025/03414 ,  H04L2025/03426 ,  H04L2027/0016

Abstract: A system for determining in-phase and quadrature-phase mismatch in a multiple-input, multiple-output (MIMO) communication architecture includes at least one transmitter coupled to at least one receiver and an in-phase (I) signal, quadrature-phase (Q) signal mismatch element configured to receive I and Q signal components over at least one communication channel, the I/Q signal mismatch element also configured to provide a signal representing gain imbalance, a signal representing quadrature error and a signal representing I/Q offset.

Abstract translation: 用于确定多输入多输出（MIMO）通信架构中的同相和正交相位失配的系统包括耦合到至少一个接收机的至少一个发射机和同相（I）信号，正交相位 （Q）信号失配元件，被配置为通过至少一个通信信道接收I和Q信号分量，I / Q信号失配元件还被配置为提供表示增益不平衡的信号，表示正交误差的信号和表示I / Q的信号 抵消。

公开(公告)号：US09049091B2

公开(公告)日：2015-06-02

申请号：US12021388

申请日：2008-01-29

Applicant: Ziquan Bai ,  Hongwei Kong ,  Ya Jing

Inventor： Ziquan Bai ,  Hongwei Kong ,  Ya Jing

IPC: H04L27/00 ,  H04L27/38

CPC classification number: H04L27/3863

Abstract: A system for determining a time delay between an in-phase signal component and a quadrature-phase signal component includes an in-phase signal start time determination module coupled to an in-phase delay module, the in-phase signal start time determination module and the in-phase delay module configured to receive an in-phase signal component of a received signal. The in-phase signal start time determination module is configured to receive a reference signal. The system also includes a quadrature-phase signal start time determination module coupled to a quadrature-phase delay module, the quadrature-phase signal start time determination module and the quadrature-phase delay module configured to receive a quadrature-phase signal component of a received signal. The quadrature-phase signal start time determination module is configured to receive a reference signal, wherein the in-phase delay module is configured to develop an in-phase delay signal and the quadrature-phase delay module is configured to develop a quadrature-phase delay signal.

Abstract translation: 用于确定同相信号分量和正交相位信号分量之间的时间延迟的系统包括耦合到同相延迟模块的同相信号开始时间确定模块，同相信号开始时间确定模块和 同相延迟模块被配置为接收接收信号的同相信号分量。 同相信号开始时间确定模块被配置为接收参考信号。 该系统还包括耦合到正交相位延迟模块的正交相位信号开始时间确定模块，正交相位信号开始时间确定模块和正交相位延迟模块，其被配置为接收所接收的正交相位信号的正交相位信号分量 信号。 正交相位信号开始时间确定模块被配置为接收参考信号，其中同相延迟模块被配置为开发同相延迟信号，并且正交相位延迟模块被配置为产生正交相位延迟 信号。

公开(公告)号：US20130050075A1

公开(公告)日：2013-02-28

申请号：US13558568

申请日：2012-07-26

Applicant: Jaoching LIN ,  Linabel CHU ,  Gary LEE ,  Chang-Hong CHEN ,  Ya-Jing WU

Inventor： Jaoching LIN ,  Linabel CHU ,  Gary LEE ,  Chang-Hong CHEN ,  Ya-Jing WU

IPC: G09G5/08

CPC classification number: H03K17/98 ,  G06F3/0338

Abstract: A capacitive pointing device includes a capacitive sensor unit, a switch unit, and an operating unit. The capacitive sensor unit has a receiving space receiving the switch unit, and a plurality of capacitive sensors disposed around the receiving space. The operating unit is spaced apart from the capacitive sensors, and is configured to result in a capacitance effect with the capacitive sensors. The operating unit is movable toward the capacitive sensor unit to trigger the switch unit, and is movable horizontally relative to the capacitive sensors. Capacitance variation between the operating unit and each of the capacitive sensors is used for determining a moving direction and an amount of movement of the operating unit.

Abstract translation: 电容性指示装置包括电容式传感器单元，开关单元和操作单元。 电容式传感器单元具有接收开关单元的接收空间和设置在接收空间周围的多个电容式传感器。 操作单元与电容传感器间隔开，并且被配置成导致电容传感器的电容效应。 操作单元可朝向电容式传感器单元移动以触发开关单元，并且可相对于电容式传感器水平移动。 操作单元和每个电容式传感器之间的电容变化用于确定操作单元的移动方向和移动量。

公开(公告)号：US20120137179A1

公开(公告)日：2012-05-31

申请号：US13070901

申请日：2011-03-24

Applicant: Chih-Jen Chin ,  Xue-Shan Han ,  Ya-Jing Fan ,  Chih-Feng Chen

Inventor： Chih-Jen Chin ,  Xue-Shan Han ,  Ya-Jing Fan ,  Chih-Feng Chen

IPC: G06F11/22

CPC classification number: G06F11/2284

Abstract: A processing system for monitoring the power-on self-test information is used for monitoring an operating state of a complex programmable logic device (CPLD) of a main board. The processing system includes a basic input/output system (BIOS) device, a CPLD and a monitoring device. The BIOS device sends power-on self-test information at a first frequency. The CPLD is electrically connected to the BIOS device. The CPLD further includes a first in first out (FIFO) register, and the FIFO register is used for storing the received power-on self-test information. The CPLD sends the power-on self-test information stored in the FIFO register at a second frequency. The monitoring device is electrically connected to the CPLD. The monitoring device is used for receiving the power-on self-test information sent from the CPLD.

Abstract translation: 用于监视上电自检信息的处理系统用于监视主板的复杂可编程逻辑器件（CPLD）的工作状态。 处理系统包括基本输入/输出系统（BIOS）设备，CPLD和监视设备。 BIOS设备以第一个频率发送开机自检信息。 CPLD电连接到BIOS设备。 CPLD进一步包括先进先出（FIFO）寄存器，FIFO寄存器用于存储接收到的开机自检信息。 CPLD以第二个频率发送存储在FIFO寄存器中的上电自检信息。 监控设备电连接到CPLD。 监控设备用于接收从CPLD发送的开机自检信息。

公开(公告)号：US20090037163A1

公开(公告)日：2009-02-05

申请号：US11830187

申请日：2007-07-30

Applicant: Hong Wei Kong ,  Honggang Zhang ,  Ya Jing ,  Ziquan Bai

Inventor： Hong Wei Kong ,  Honggang Zhang ,  Ya Jing ,  Ziquan Bai

IPC: G06F9/44

CPC classification number: G06F9/455

Abstract: A simulation system for a communication system includes a user interface to receive user definition and system configuration parameters of a simulation configuration file that includes a plurality of data structures representing various functional modules of the simulated communication system. A model library is provided to store different implementation models corresponding to different communication standards for each of the functional modules. A parsing module accesses the model library according to the user definition and system configuration parameters to obtain the appropriate implementation model for each of the functional modules, and generates a simulated system program based on the selected implementation models such that the simulated system program is reconfigurable to different implementations and communication standards. A simulation engine runs the simulated system program to simulate the simulated communication system. A simulated system program generation system is also described.

Abstract translation: 用于通信系统的模拟系统包括用于接收模拟配置文件的用户定义和系统配置参数的用户界面，该模拟配置文件包括表示模拟通信系统的各种功能模块的多个数据结构。 提供模型库以存储对应于每个功能模块的不同通信标准的不同实现模型。 分析模块根据用户定义和系统配置参数访问模型库，以获得每个功能模块的适当实现模型，并且基于所选择的实现模型生成模拟系统程序，使得模拟系统程序可重新配置为 不同的实现和通信标准。 模拟引擎运行模拟系统程序来模拟仿真通信系统。 还描述了一种模拟系统程序生成系统。

公开(公告)号：US20120137027A1

公开(公告)日：2012-05-31

申请号：US13070836

申请日：2011-03-24

Applicant: Quan-Jie Zheng ,  Chih-Jen Chin ,  Ya-Jing Fan ,  Chih-Feng Chen

Inventor： Quan-Jie Zheng ,  Chih-Jen Chin ,  Ya-Jing Fan ,  Chih-Feng Chen

IPC: G06F3/00

CPC classification number: G06F11/3041 ,  G06F11/3055 ,  G06F11/3068

Abstract: A system and method for monitoring an input/output port status of peripheral devices are used for monitoring an operating status of each peripheral device of a main board. The system includes at least one peripheral device, a complex programmable logic device (CPLD), and an output apparatus. The CPLD is electrically connected to the peripheral devices. The CPLD further includes a protocol conversion unit and multiple data registers. The protocol conversion unit converts an operating status of the CPLD or the peripheral devices into device status information. The data register is used for storing the device status information. The output apparatus is electrically connected to the CPLD. The output apparatus is used for displaying the device status information in the data register. A user can observe the operating status of each of the peripheral devices of the main board conveniently.

Abstract translation: 用于监视外围设备的输入/输出端口状态的系统和方法用于监控主板的每个外围设备的操作状态。 该系统包括至少一个外围设备，复杂可编程逻辑器件（CPLD）和输出设备。 CPLD电连接到外围设备。 CPLD还包括协议转换单元和多个数据寄存器。 协议转换单元将CPLD或外围设备的操作状态转换为设备状态信息。 数据寄存器用于存储设备状态信息。 输出装置电连接到CPLD。 输出装置用于在数据寄存器中显示设备状态信息。 用户可以方便地观察主板各外围设备的运行状态。

公开(公告)号：US20090190705A1

公开(公告)日：2009-07-30

申请号：US12021388

申请日：2008-01-29

Applicant: Ziquan Bai ,  Hongwei Kong ,  Ya Jing

Inventor： Ziquan Bai ,  Hongwei Kong ,  Ya Jing

IPC: H04L7/00

CPC classification number: H04L27/3863

Abstract: A system for determining a time delay between an in-phase signal component and a quadrature-phase signal component includes an in-phase signal start time determination module coupled to an in-phase delay module, the in-phase signal start time determination module and the in-phase delay module configured to receive an in-phase signal component of a received signal. The in-phase signal start time determination module is configured to receive a reference signal. The system also includes a quadrature-phase signal start time determination module coupled to a quadrature-phase delay module, the quadrature-phase signal start time determination module and the quadrature-phase delay module configured to receive a quadrature-phase signal component of a received signal. The quadrature-phase signal start time determination module is configured to receive a reference signal, wherein the in-phase delay module is configured to develop an in-phase delay signal and the quadrature-phase delay module is configured to develop a quadrature-phase delay signal.

Abstract translation: 用于确定同相信号分量和正交相位信号分量之间的时间延迟的系统包括耦合到同相延迟模块的同相信号开始时间确定模块，同相信号开始时间确定模块和 同相延迟模块被配置为接收接收信号的同相信号分量。 同相信号开始时间确定模块被配置为接收参考信号。 该系统还包括耦合到正交相位延迟模块的正交相位信号开始时间确定模块，正交相位信号开始时间确定模块和正交相位延迟模块，其被配置为接收所接收的正交相位信号的正交相位信号分量 信号。 正交相位信号开始时间确定模块被配置为接收参考信号，其中同相延迟模块被配置为开发同相延迟信号，并且正交相位延迟模块被配置为产生正交相位延迟 信号。

公开(公告)号：USD581534S1

公开(公告)日：2008-11-25

申请号：US29283615

申请日：2007-08-18

Applicant: Baoku Liu Dong ,  Ya Jing Dong

Designer： Baoku Liu Dong ,  Ya Jing Dong