公开(公告)号：US08471753B1

公开(公告)日：2013-06-25

申请号：US13034813

申请日：2011-02-25

Applicant: Yen-Chuan Huang ,  Tai-Cheng Lee

Inventor： Yen-Chuan Huang ,  Tai-Cheng Lee

IPC: H03M1/38

CPC classification number: H03M1/1225 ,  H03M1/168

Abstract: A pipelined analog-to-digital converter with less power consumption is provided. In one embodiment, the pipelined analog-to-digital converter comprises a first stage, a second stage, and a third stage. The first stage receives a first stage input signal to derive a first stage output signal and a first residue. The second stage receives a second stage input signal to derive a second stage output signal and a second residue, wherein the second stage input signal corresponds to the first residue. The third stage receives a third stage input signal to derive a third stage output signal and a third residue, wherein the third stage input signal corresponds to the second residue. The first, second and third stages share an operational amplifier by utilizing at least three phases to control the operational amplifier.

Abstract translation: 提供了具有较少功耗的流水线模数转换器。 在一个实施例中，流水线模数转换器包括第一级，第二级和第三级。 第一级接收第一级输入信号以导出第一级输出信号和第一级残差。 第二级接收第二级输入信号以导出第二级输出信号和第二残差，其中第二级输入信号对应于第一级残差。 第三级接收第三级输入信号以导出第三级输出信号和第三残差，其中第三级输入信号对应于第二级残差。 第一，第二和第三级通过利用至少三个相位来控制运算放大器来共享运算放大器。