COMPOSITE PLATE STRUCTURE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    COMPOSITE PLATE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    复合板结构及其制造方法

    公开(公告)号:US20130108830A1

    公开(公告)日:2013-05-02

    申请号:US13654431

    申请日:2012-10-18

    IPC分类号: B32B3/26 B32B37/12

    摘要: A composite plate structure including a fiber composite sheet, a metal layer, and a resin layer is provided. The fiber composite sheet includes a first fiber layer, a core layer, and a second fiber layer. The core layer is disposed between the first fiber layer and the second fiber layer. The metal layer is disposed on the fiber composite sheet and has at least one opening. A portion of the second fiber layer is located in the opening. The resin layer is disposed on the metal layer. In addition, a manufacturing method of the composite plate structure is also provided.

    摘要翻译: 提供了包括纤维复合片,金属层和树脂层的复合板结构。 纤维复合片包括第一纤维层,芯层和第二纤维层。 芯层设置在第一纤维层和第二纤维层之间。 金属层设置在纤维复合片材上,并具有至少一个开口。 第二纤维层的一部分位于开口中。 树脂层设置在金属层上。 此外,还提供了复合板结构的制造方法。

    Diagnosis framework to shorten yield learning cycles of advanced processes
    3.
    发明授权
    Diagnosis framework to shorten yield learning cycles of advanced processes 有权
    诊断框架来缩短先进过程的产量学习周期

    公开(公告)号:US09310431B2

    公开(公告)日:2016-04-12

    申请号:US13588155

    申请日:2012-08-17

    摘要: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).

    摘要翻译: 本公开涉及一种诊断框架,用于缩短从高缺陷密度阶段到技术成熟度的技术节点制造过程的产量学习周期。 多个待测缺陷(DUT)结构被设计为捕获与缺陷形成相关的潜在制造问题。 通过将DUT结构布置在DUT载体单元内而形成测试结构,该DUT载体单元已经通过启发式产量分析进行了屈服强化,使得DUT载体单元的缺陷密度基本上为零。 在DUT载体单元中的DUT结构内形成的缺陷相关联的测试模式和各种故障情形的应用的可能结果被模拟并存储在查找表(LUT)中。 然后可以参考LUT以确定测试结构内的缺陷的位置,而不需要迭代分析来正确地选择用于物理故障分析(PFA)的缺陷候选。

    Diagnosis Framework to Shorten Yield Learning Cycles of Advanced Processes
    4.
    发明申请
    Diagnosis Framework to Shorten Yield Learning Cycles of Advanced Processes 有权
    诊断框架,缩短先进过程的产量学习周期

    公开(公告)号:US20140049281A1

    公开(公告)日:2014-02-20

    申请号:US13588155

    申请日:2012-08-17

    IPC分类号: G01R31/02 G06F17/50

    摘要: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).

    摘要翻译: 本公开涉及一种诊断框架,用于缩短从高缺陷密度阶段到技术成熟度的技术节点制造过程的产量学习周期。 多个待测缺陷(DUT)结构被设计为捕获与缺陷形成相关的潜在制造问题。 通过将DUT结构布置在DUT载体单元内而形成测试结构,该DUT载体单元已经通过启发式产量分析进行了屈服强化,使得DUT载体单元的缺陷密度基本上为零。 在DUT载体单元中的DUT结构内形成的缺陷相关联的测试模式和各种故障情形的应用的可能结果被模拟并存储在查找表(LUT)中。 然后可以参考LUT以确定测试结构内的缺陷的位置,而不需要迭代分析来正确地选择用于物理故障分析(PFA)的缺陷候选。