公开(公告)号：US09310431B2

公开(公告)日：2016-04-12

申请号：US13588155

申请日：2012-08-17

申请人： Yen-Ling Liu ,  Nan-Hsin Tseng ,  Ji-Jan Chen ,  Wei-Pin Changchien ,  Samuel C. Pan

发明人： Yen-Ling Liu ,  Nan-Hsin Tseng ,  Ji-Jan Chen ,  Wei-Pin Changchien ,  Samuel C. Pan

IPC分类号： G01R31/302 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/02

CPC分类号： G01R31/31704 ,  G01R31/025 ,  G01R31/318357

摘要： The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).

摘要翻译： 本公开涉及一种诊断框架，用于缩短从高缺陷密度阶段到技术成熟度的技术节点制造过程的产量学习周期。 多个待测缺陷（DUT）结构被设计为捕获与缺陷形成相关的潜在制造问题。 通过将DUT结构布置在DUT载体单元内而形成测试结构，该DUT载体单元已经通过启发式产量分析进行了屈服强化，使得DUT载体单元的缺陷密度基本上为零。 在DUT载体单元中的DUT结构内形成的缺陷相关联的测试模式和各种故障情形的应用的可能结果被模拟并存储在查找表（LUT）中。 然后可以参考LUT以确定测试结构内的缺陷的位置，而不需要迭代分析来正确地选择用于物理故障分析（PFA）的缺陷候选。

公开(公告)号：US20140049281A1

公开(公告)日：2014-02-20

申请号：US13588155

申请日：2012-08-17

申请人： Yen-Ling Liu ,  Nan-Hsin Tseng ,  Ji-Jan Chen ,  Wei-Pin Changchien ,  Samuel C. Pan

发明人： Yen-Ling Liu ,  Nan-Hsin Tseng ,  Ji-Jan Chen ,  Wei-Pin Changchien ,  Samuel C. Pan

IPC分类号： G01R31/02 ,  G06F17/50

CPC分类号： G01R31/31704 ,  G01R31/025 ,  G01R31/318357

摘要： The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).

摘要翻译： 本公开涉及一种诊断框架，用于缩短从高缺陷密度阶段到技术成熟度的技术节点制造过程的产量学习周期。 多个待测缺陷（DUT）结构被设计为捕获与缺陷形成相关的潜在制造问题。 通过将DUT结构布置在DUT载体单元内而形成测试结构，该DUT载体单元已经通过启发式产量分析进行了屈服强化，使得DUT载体单元的缺陷密度基本上为零。 在DUT载体单元中的DUT结构内形成的缺陷相关联的测试模式和各种故障情形的应用的可能结果被模拟并存储在查找表（LUT）中。 然后可以参考LUT以确定测试结构内的缺陷的位置，而不需要迭代分析来正确地选择用于物理故障分析（PFA）的缺陷候选。

公开(公告)号：US08113412B1

公开(公告)日：2012-02-14

申请号：US13107476

申请日：2011-05-13

申请人： Nan-Hsin Tseng ,  Yun-Han Lee ,  Chin-Chou Liu ,  Ji-Jan Chen ,  Wei-Pin Changchien ,  Chien-Hui Chen

发明人： Nan-Hsin Tseng ,  Yun-Han Lee ,  Chin-Chou Liu ,  Ji-Jan Chen ,  Wei-Pin Changchien ,  Chien-Hui Chen

IPC分类号： B23K31/02 ,  B23K31/12

CPC分类号： G01R31/2853 ,  G01R31/307

摘要： A method includes electrically grounding a first plurality of metal bumps on a first surface of an interconnection component to a common ground plate. A voltage contrast (VC) image of a second plurality of metal bumps of the interconnection component is generated. Grey levels of the second plurality of metal bumps in the VC image are analyzed to find defect connections between the second plurality of metal bumps and respective ones of the first plurality of metal bumps.

摘要翻译： 一种方法包括将互连部件的第一表面上的第一多个金属凸块电接地到公共接地板。 产生互连部件的第二多个金属凸块的电压对比度（VC）图像。 分析VC图像中的第二多个金属凸块的灰度级，以发现第二多个金属凸块和第一多个金属凸块中的相应的金属凸块之间的缺陷连接。

公开(公告)号：US08384430B2

公开(公告)日：2013-02-26

申请号：US12971204

申请日：2010-12-17

申请人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Wei-Pin Changchien ,  Pei-Ying Lin ,  Ta-Wen Hung

发明人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Wei-Pin Changchien ,  Pei-Ying Lin ,  Ta-Wen Hung

IPC分类号： H03K19/21 ,  H03K17/00

CPC分类号： H03K19/23 ,  G01R31/31816 ,  H03K19/17764

摘要： A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units.

摘要翻译： 芯片包括贯穿芯片的衬底的多个贯穿衬底通孔（TSV），其中多个TSV被分组为多个TSV对。 多个接触焊盘耦合到多个TSV，其中多个接触焊盘暴露在管芯的第一表面上。 芯片还包括多个平衡脉冲比较单元，其中多个平衡脉冲比较单元中的每一个包括耦合到多个TSV对之一的第一TSV和第二TSV的第一输入和第二输入。 芯片还包括多个脉冲锁存器，每个脉冲锁存器包括耦合到多个平衡脉冲比较单元之一的输出的输入端。

公开(公告)号：US20110121856A1

公开(公告)日：2011-05-26

申请号：US12857270

申请日：2010-08-16

申请人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Wei-Pin Changchien ,  Kin Lam Tong

发明人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Wei-Pin Changchien ,  Kin Lam Tong

IPC分类号： H03K19/00 ,  H03K19/23

CPC分类号： H03K19/23 ,  G01R31/31816

摘要： A system and method for detecting soft-failures in integrated circuits is provided. A circuit includes a combinatorial logic block having a first signal input and a second signal input, and a latch coupled to an output of the combinatorial logic block. The combinatorial logic block produces a pulse when only one of either a first signal provided by the first signal input or a second signal provided by the second signal input is a logical high value, and the latch captures the pulse if the pulse has a pulse width greater than a second threshold. The pulse has a pulse width that is based on a timing difference between a first signal transition on the first signal and a second signal transition on the second signal, the combinatorial logic block produces the pulse if the timing difference is greater than a first threshold, and the combinatorial logic block operates with balanced inputs.

摘要翻译： 提供一种用于检测集成电路中的软故障的系统和方法。 电路包括具有第一信号输入和第二信号输入的组合逻辑块，以及耦合到组合逻辑块的输出的锁存器。 当仅由第一信号输入提供的第一信号或由第二信号输入提供的第二信号中的一个信号是逻辑高值时，组合逻辑块产生脉冲，并且如果脉冲具有脉冲宽度，则锁存器捕捉脉冲 大于第二阈值。 脉冲具有基于第一信号上的第一信号转换与第二信号上的第二信号转换之间的定时差的脉冲宽度，如果定时差大于第一阈值，组合逻辑块产生脉冲， 并且组合逻辑块通过平衡输入进行操作。

公开(公告)号：US08339155B2

公开(公告)日：2012-12-25

申请号：US12857270

申请日：2010-08-16

申请人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Wei-Pin Changchien ,  Kin Lam Tong

发明人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Wei-Pin Changchien ,  Kin Lam Tong

IPC分类号： H03K19/00 ,  H03K19/23

CPC分类号： H03K19/23 ,  G01R31/31816

摘要： A system and method for detecting soft-failures in integrated circuits is provided. A circuit includes a combinatorial logic block having a first signal input and a second signal input, and a latch coupled to an output of the combinatorial logic block. The combinatorial logic block produces a pulse when only one of either a first signal provided by the first signal input or a second signal provided by the second signal input is a logical high value, and the latch captures the pulse if the pulse has a pulse width greater than a second threshold. The pulse has a pulse width that is based on a timing difference between a first signal transition on the first signal and a second signal transition on the second signal, the combinatorial logic block produces the pulse if the timing difference is greater than a first threshold, and the combinatorial logic block operates with balanced inputs.

摘要翻译： 提供一种用于检测集成电路中的软故障的系统和方法。 电路包括具有第一信号输入和第二信号输入的组合逻辑块，以及耦合到组合逻辑块的输出的锁存器。 当仅由第一信号输入提供的第一信号或由第二信号输入提供的第二信号中的一个信号是逻辑高值时，组合逻辑块产生脉冲，并且如果脉冲具有脉冲宽度，则锁存器捕捉脉冲 大于第二阈值。 脉冲具有基于第一信号上的第一信号转换与第二信号上的第二信号转换之间的定时差的脉冲宽度，如果定时差大于第一阈值，组合逻辑块产生脉冲， 并且组合逻辑块通过平衡输入进行操作。

公开(公告)号：US20120038388A1

公开(公告)日：2012-02-16

申请号：US12971204

申请日：2010-12-17

申请人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Wei-Pin Changchien ,  Pei-Ying Lin ,  Ta-Wen Hung

发明人： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Wei-Pin Changchien ,  Pei-Ying Lin ,  Ta-Wen Hung

IPC分类号： H03K19/21 ,  H03K17/00

CPC分类号： H03K19/23 ,  G01R31/31816 ,  H03K19/17764

摘要： A die includes a plurality of through-substrate vias (TSVs) penetrating a substrate of the die, wherein the plurality of TSVs are grouped as a plurality of TSV pairs. A plurality of contact pads is coupled to the plurality of TSVs, wherein the plurality of contact pads is exposed on a first surface of the die. The die further includes a plurality of balanced pulse comparison units, wherein each of the plurality of balanced pulse comparison units includes a first input and a second input coupled to a first TSV and a second TSV of one of the plurality of TSV pairs. The die further includes a plurality of pulse latches, each including an input coupled to an output of one of the plurality of balanced pulse comparison units.

摘要翻译： 芯片包括贯穿芯片的衬底的多个贯穿衬底通孔（TSV），其中多个TSV被分组为多个TSV对。 多个接触焊盘耦合到多个TSV，其中多个接触焊盘暴露在模具的第一表面上。 芯片还包括多个平衡脉冲比较单元，其中多个平衡脉冲比较单元中的每一个包括耦合到多个TSV对之一的第一TSV和第二TSV的第一输入和第二输入。 芯片还包括多个脉冲锁存器，每个脉冲锁存器包括耦合到多个平衡脉冲比较单元之一的输出的输入端。

公开(公告)号：US08566766B2

公开(公告)日：2013-10-22

申请号：US12943379

申请日：2010-11-10

申请人： Sandeep Kumar Goel ,  Saurabh Gupta ,  Wei-Pin Changchien ,  Chin-Chou Liu

发明人： Sandeep Kumar Goel ,  Saurabh Gupta ,  Wei-Pin Changchien ,  Chin-Chou Liu

IPC分类号： G06F17/50

CPC分类号： G01R31/318328

摘要： System and method for effectively detecting small delay defects is disclosed. The method first loads layout information of an integrated circuit. Then, the nets and paths of the integrated circuit are partitioned into two groups based upon their physical information. The physical information comprises the length of each path and net and the number of vias at each path and net. A timing-aware automatic test pattern generator is configured to generate test patterns for the first group having paths and nets susceptible to small delay defects. A traditional transition delay fault test pattern generator is configured to generate test patterns for the second group.

摘要翻译： 公开了用于有效检测小延迟缺陷的系统和方法。 该方法首先加载集成电路的布局信息。 然后，基于它们的物理信息将集成电路的网络和路径划分成两组。 物理信息包括每个路径和网络的长度以及每个路径和网络处的通道数量。 定时感知自动测试模式发生器被配置为产生具有易受小延迟缺陷影响的路径和网络的第一组的测试模式。 传统的转换延迟故障测试模式发生器被配置为产生第二组的测试模式。

公开(公告)号：US08347132B2

公开(公告)日：2013-01-01

申请号：US12619428

申请日：2009-11-16

申请人： Lee-Chung Lu ,  Chung-Hsing Wang ,  Myron Shak ,  Wei-Pin Changchien ,  Kuo-Yin Chen ,  Chi Wei Hu ,  Kevin Hung ,  Wu-An Kuo

发明人： Lee-Chung Lu ,  Chung-Hsing Wang ,  Myron Shak ,  Wei-Pin Changchien ,  Kuo-Yin Chen ,  Chi Wei Hu ,  Kevin Hung ,  Wu-An Kuo

IPC分类号： G06F1/00

CPC分类号： G06F1/3287 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

摘要： A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module.

摘要翻译： 公开了一种用于减少处理器中的有功功率的系统和方法。 方法实施例包括以下步骤：确定特定逻辑块何时不活动，确定特定逻辑块的供电状态，将特定逻辑块与主处理器内核隔离，以及断开特定逻辑块。 当系统需要特定逻辑块时，该方法还包括重新激活该块。 系统实施例包括耦合到时钟控制模块，隔离控制模块和报头/页脚模块的软件和处理器，其可操作以隔离特定逻辑块并关闭特定逻辑块，从而降低功率。 另一个实施例包括通过时钟门控模块耦合到时钟的逻辑模块，用于隔离逻辑模块的隔离模块，用于禁止对逻辑模块供电的报头/页脚模块，以及用于控制时钟的电源和时钟门控控制模块 门控模块和页眉/页脚模块。

公开(公告)号：US08701070B2

公开(公告)日：2014-04-15

申请号：US13613678

申请日：2012-09-13

申请人： Yi-Lin Chuang ,  Chun-Cheng Ku ,  Yun-Han Lee ,  Shao-Yu Wang ,  Wei-Pin Changchien ,  Chin-Chou Liu

发明人： Yi-Lin Chuang ,  Chun-Cheng Ku ,  Yun-Han Lee ,  Shao-Yu Wang ,  Wei-Pin Changchien ,  Chin-Chou Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

摘要翻译： 除此之外，本文提供了一种或多种用于定义用于集成电路的相关单元的组边界框并且为包括组边界框的集成电路生成新布局的系统和技术。 也就是说，基于相关单元的位置值来定义一个或多个组边界框。 基于诸如考虑线长度，定时和单元密度的目标函数的放置技术，将这样的组边界框放置在新布局内。 一个或多个组边界框的大小或重新形状以减少新布局中的单元格重叠。 以这种方式，新布局包括根据减轻集成电路的线长度和定时延迟的配置放置在新布局内的由一个或多个组边界框绑定的相关单元。