公开(公告)号：US08988954B2

公开(公告)日：2015-03-24

申请号：US13612953

申请日：2012-09-13

申请人： Yew K Chong ,  Sanjay Mangal

发明人： Yew K Chong ,  Sanjay Mangal

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C7/06 ,  G11C7/10 ,  G11C11/409 ,  G11C5/02 ,  G11C7/02 ,  G11C7/22 ,  G11C11/419

CPC分类号： G11C7/12 ,  G11C5/025 ,  G11C7/02 ,  G11C7/06 ,  G11C7/10 ,  G11C7/1048 ,  G11C7/222 ,  G11C11/409 ,  G11C11/419

摘要： A memory device is provided comprising an array of memory cells. During a read operation, voltage on a read bit line will transition towards a second voltage level if a data value stored in that activated memory cell has a first value, and sense amplifier circuitry will then detect this situation. If that situation is not detected, the sense amplifier circuitry determines that the activated memory cell stores a second value. Bit line keeper circuitry is coupled to each read bit line and is responsive to an asserted keeper pulse signal to pull the voltage on each read bit line towards the first voltage level. Keeper pulse signal generation circuitry asserts the keeper pulse signal at a selected time. The selected time is such that the voltage on the associated read bit line will have transitioned to the trip voltage level before the keeper pulse signal is asserted.

摘要翻译： 提供了包括存储器单元阵列的存储器件。 在读取操作期间，如果存储在该激活的存储单元中的数据值具有第一值，则读位线上的电压将转变到第二电压电平，并且读出放大器电路将检测到这种情况。 如果没有检测到这种情况，则感测放大器电路确定激活的存储单元存储第二值。 位线保持器电路耦合到每个读位线，并且响应于断言的保持器脉冲信号以将每个读取位线上的电压拉向第一电压电平。 保持器脉冲信号发生电路在选定的时间断开保持器脉冲信号。 所选择的时间使得相关读取位线上的电压将在保持器脉冲信号被置位之前已经转变到跳闸电压电平。